1 //===- ARMRegisterInfo.td - ARM Register defs -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the ARM register file
12 //===----------------------------------------------------------------------===//
14 // Registers are identified with 4-bit ID numbers.
15 class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
17 let Namespace = "ARM";
18 let SubRegs = subregs;
21 class ARMFReg<bits<5> num, string n> : Register<n> {
23 let Namespace = "ARM";
27 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
28 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
29 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
30 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
31 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
32 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
33 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
34 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
35 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
36 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
37 def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
38 def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
39 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
40 def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
41 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
42 def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
45 def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
46 def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">;
47 def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">;
48 def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">;
49 def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">;
50 def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
51 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
52 def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
53 def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
54 def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
55 def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
56 def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
57 def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
58 def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
59 def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
60 def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
62 // Aliases of the F* registers used to hold 64-bit fp values (doubles)
63 def D0 : ARMReg< 0, "d0", [S0, S1]>;
64 def D1 : ARMReg< 1, "d1", [S2, S3]>;
65 def D2 : ARMReg< 2, "d2", [S4, S5]>;
66 def D3 : ARMReg< 3, "d3", [S6, S7]>;
67 def D4 : ARMReg< 4, "d4", [S8, S9]>;
68 def D5 : ARMReg< 5, "d5", [S10, S11]>;
69 def D6 : ARMReg< 6, "d6", [S12, S13]>;
70 def D7 : ARMReg< 7, "d7", [S14, S15]>;
71 def D8 : ARMReg< 8, "d8", [S16, S17]>;
72 def D9 : ARMReg< 9, "d9", [S18, S19]>;
73 def D10 : ARMReg<10, "d10", [S20, S21]>;
74 def D11 : ARMReg<11, "d11", [S22, S23]>;
75 def D12 : ARMReg<12, "d12", [S24, S25]>;
76 def D13 : ARMReg<13, "d13", [S26, S27]>;
77 def D14 : ARMReg<14, "d14", [S28, S29]>;
78 def D15 : ARMReg<15, "d15", [S30, S31]>;
80 // VFP3 defines 16 additional double registers
81 def D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d17">;
82 def D18 : ARMFReg<18, "d18">; def D19 : ARMFReg<19, "d19">;
83 def D20 : ARMFReg<20, "d20">; def D21 : ARMFReg<21, "d21">;
84 def D22 : ARMFReg<22, "d22">; def D23 : ARMFReg<23, "d23">;
85 def D24 : ARMFReg<24, "d24">; def D25 : ARMFReg<25, "d25">;
86 def D26 : ARMFReg<26, "d26">; def D27 : ARMFReg<27, "d27">;
87 def D28 : ARMFReg<28, "d28">; def D29 : ARMFReg<29, "d29">;
88 def D30 : ARMFReg<30, "d30">; def D31 : ARMFReg<31, "d31">;
90 // Advanced SIMD (NEON) defines 16 quad-word aliases
91 def Q0 : ARMReg< 0, "q0", [D0, D1]>;
92 def Q1 : ARMReg< 1, "q1", [D2, D3]>;
93 def Q2 : ARMReg< 2, "q2", [D4, D5]>;
94 def Q3 : ARMReg< 3, "q3", [D6, D7]>;
95 def Q4 : ARMReg< 4, "q4", [D8, D9]>;
96 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
97 def Q6 : ARMReg< 6, "q6", [D12, D13]>;
98 def Q7 : ARMReg< 7, "q7", [D14, D15]>;
99 def Q8 : ARMReg< 8, "q8", [D16, D17]>;
100 def Q9 : ARMReg< 9, "q9", [D18, D19]>;
101 def Q10 : ARMReg<10, "q10", [D20, D21]>;
102 def Q11 : ARMReg<11, "q11", [D22, D23]>;
103 def Q12 : ARMReg<12, "q12", [D24, D25]>;
104 def Q13 : ARMReg<13, "q13", [D26, D27]>;
105 def Q14 : ARMReg<14, "q14", [D28, D29]>;
106 def Q15 : ARMReg<15, "q15", [D30, D31]>;
108 // Current Program Status Register.
109 def CPSR : ARMReg<0, "cpsr">;
111 def FPSCR : ARMReg<1, "fpscr">;
115 // pc == Program Counter
116 // lr == Link Register
117 // sp == Stack Pointer
118 // r12 == ip (scratch)
119 // r7 == Frame Pointer (thumb-style backtraces)
120 // r9 == May be reserved as Thread Register
121 // r11 == Frame Pointer (arm-style backtraces)
122 // r10 == Stack Limit
124 def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
125 R7, R8, R9, R10, R12, R11,
127 let MethodProtos = [{
128 iterator allocation_order_begin(const MachineFunction &MF) const;
129 iterator allocation_order_end(const MachineFunction &MF) const;
131 // FIXME: We are reserving r12 in case the PEI needs to use it to
132 // generate large stack offset. Make it available once we have register
133 // scavenging. Similarly r3 is reserved in Thumb mode for now.
134 let MethodBodies = [{
135 // FP is R11, R9 is available.
136 static const unsigned ARM_GPR_AO_1[] = {
137 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
139 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
140 ARM::R8, ARM::R9, ARM::R10,
142 // FP is R11, R9 is not available.
143 static const unsigned ARM_GPR_AO_2[] = {
144 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
146 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
149 // FP is R7, R9 is available as non-callee-saved register.
150 // This is used by Darwin.
151 static const unsigned ARM_GPR_AO_3[] = {
152 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
153 ARM::R9, ARM::R12,ARM::LR,
154 ARM::R4, ARM::R5, ARM::R6,
155 ARM::R8, ARM::R10,ARM::R11,ARM::R7 };
156 // FP is R7, R9 is not available.
157 static const unsigned ARM_GPR_AO_4[] = {
158 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
160 ARM::R4, ARM::R5, ARM::R6,
161 ARM::R8, ARM::R10,ARM::R11,
163 // FP is R7, R9 is available as callee-saved register.
164 // This is used by non-Darwin platform in Thumb mode.
165 static const unsigned ARM_GPR_AO_5[] = {
166 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
168 ARM::R4, ARM::R5, ARM::R6,
169 ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
172 GPRClass::allocation_order_begin(const MachineFunction &MF) const {
173 const TargetMachine &TM = MF.getTarget();
174 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
175 if (Subtarget.isTargetDarwin()) {
176 if (Subtarget.isR9Reserved())
181 if (Subtarget.isR9Reserved())
183 else if (Subtarget.isThumb())
191 GPRClass::allocation_order_end(const MachineFunction &MF) const {
192 const TargetMachine &TM = MF.getTarget();
193 const TargetRegisterInfo *RI = TM.getRegisterInfo();
194 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
195 GPRClass::iterator I;
197 if (Subtarget.isTargetDarwin()) {
198 if (Subtarget.isR9Reserved())
199 I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
201 I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
203 if (Subtarget.isR9Reserved())
204 I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
205 else if (Subtarget.isThumb())
206 I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
208 I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
211 // Mac OS X requires FP not to be clobbered for backtracing purpose.
212 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
217 // Thumb registers are R0-R7 normally. Some instructions can still use
218 // the general GPR register class above (MOV, e.g.)
219 def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
220 let MethodProtos = [{
221 iterator allocation_order_begin(const MachineFunction &MF) const;
222 iterator allocation_order_end(const MachineFunction &MF) const;
224 // FIXME: We are reserving r3 in Thumb mode in case the PEI needs to use it
225 // to generate large stack offset. Make it available once we have register
227 let MethodBodies = [{
228 static const unsigned THUMB_tGPR_AO[] = {
229 ARM::R0, ARM::R1, ARM::R2,
230 ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
232 // FP is R7, only low registers available.
234 tGPRClass::allocation_order_begin(const MachineFunction &MF) const {
235 return THUMB_tGPR_AO;
239 tGPRClass::allocation_order_end(const MachineFunction &MF) const {
240 const TargetMachine &TM = MF.getTarget();
241 const TargetRegisterInfo *RI = TM.getRegisterInfo();
242 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
243 tGPRClass::iterator I =
244 THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned));
245 // Mac OS X requires FP not to be clobbered for backtracing purpose.
246 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
251 // Scalar single precision floating point register class..
252 def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
253 S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
254 S23, S24, S25, S26, S27, S28, S29, S30, S31]>;
256 // Scalar double precision floating point / generic 64-bit vector register
258 // ARM requires only word alignment for double. It's more performant if it
259 // is double-word alignment though.
260 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
261 [D0, D1, D2, D3, D4, D5, D6, D7,
262 D8, D9, D10, D11, D12, D13, D14, D15,
263 D16, D17, D18, D19, D20, D21, D22, D23,
264 D24, D25, D26, D27, D28, D29, D30, D31]> {
265 let SubRegClassList = [SPR, SPR];
266 let MethodProtos = [{
267 iterator allocation_order_begin(const MachineFunction &MF) const;
268 iterator allocation_order_end(const MachineFunction &MF) const;
270 let MethodBodies = [{
272 static const unsigned ARM_DPR_VFP2[] = {
273 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
274 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
275 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
276 ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
278 static const unsigned ARM_DPR_VFP3[] = {
279 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
280 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
281 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
282 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
283 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
284 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
285 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
286 ARM::D28, ARM::D29, ARM::D30, ARM::D31 };
288 DPRClass::allocation_order_begin(const MachineFunction &MF) const {
289 const TargetMachine &TM = MF.getTarget();
290 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
291 if (Subtarget.hasVFP3())
297 DPRClass::allocation_order_end(const MachineFunction &MF) const {
298 const TargetMachine &TM = MF.getTarget();
299 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
300 if (Subtarget.hasVFP3())
301 return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned));
303 return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned));
308 // Generic 128-bit vector register class.
309 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
310 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
311 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> {
312 let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR];
315 // Condition code registers.
316 def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
318 //===----------------------------------------------------------------------===//
319 // Subregister Set Definitions... now that we have all of the pieces, define the
320 // sub registers for each register.
323 def arm_ssubreg_0 : PatLeaf<(i32 1)>;
324 def arm_ssubreg_1 : PatLeaf<(i32 2)>;
325 def arm_ssubreg_2 : PatLeaf<(i32 3)>;
326 def arm_ssubreg_3 : PatLeaf<(i32 4)>;
327 def arm_dsubreg_0 : PatLeaf<(i32 5)>;
328 def arm_dsubreg_1 : PatLeaf<(i32 6)>;
330 // S sub-registers of D registers.
331 def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
332 D8, D9, D10, D11, D12, D13, D14, D15],
333 [S0, S2, S4, S6, S8, S10, S12, S14,
334 S16, S18, S20, S22, S24, S26, S28, S30]>;
335 def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
336 D8, D9, D10, D11, D12, D13, D14, D15],
337 [S1, S3, S5, S7, S9, S11, S13, S15,
338 S17, S19, S21, S23, S25, S27, S29, S31]>;
340 // S sub-registers of Q registers.
341 def : SubRegSet<1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
342 [S0, S4, S8, S12, S16, S20, S24, S28]>;
343 def : SubRegSet<2, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
344 [S1, S5, S9, S13, S17, S21, S25, S29]>;
345 def : SubRegSet<3, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
346 [S2, S6, S10, S14, S18, S22, S26, S30]>;
347 def : SubRegSet<4, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
348 [S3, S7, S11, S15, S19, S23, S27, S31]>;
350 // D sub-registers of Q registers.
351 def : SubRegSet<5, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
352 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
353 [D0, D2, D4, D6, D8, D10, D12, D14,
354 D16, D18, D20, D22, D24, D26, D28, D30]>;
355 def : SubRegSet<6, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
356 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
357 [D1, D3, D5, D7, D9, D11, D13, D15,
358 D17, D19, D21, D23, D25, D27, D29, D31]>;