1 //===- ARMRegisterInfo.td - ARM Register defs -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the ARM register file
12 //===----------------------------------------------------------------------===//
14 // Registers are identified with 4-bit ID numbers.
15 class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
17 let Namespace = "ARM";
18 let SubRegs = subregs;
21 class ARMFReg<bits<6> num, string n> : Register<n> {
23 let Namespace = "ARM";
27 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
28 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
29 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
30 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
31 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
32 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
33 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
34 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
35 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
36 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
37 def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
38 def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
39 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
40 def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
41 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
42 def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
45 def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
46 def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">;
47 def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">;
48 def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">;
49 def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">;
50 def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
51 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
52 def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
53 def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
54 def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
55 def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
56 def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
57 def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
58 def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
59 def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
60 def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
61 def SDummy : ARMFReg<63, "sINVALID">;
63 // Aliases of the F* registers used to hold 64-bit fp values (doubles)
64 def D0 : ARMReg< 0, "d0", [S0, S1]>;
65 def D1 : ARMReg< 1, "d1", [S2, S3]>;
66 def D2 : ARMReg< 2, "d2", [S4, S5]>;
67 def D3 : ARMReg< 3, "d3", [S6, S7]>;
68 def D4 : ARMReg< 4, "d4", [S8, S9]>;
69 def D5 : ARMReg< 5, "d5", [S10, S11]>;
70 def D6 : ARMReg< 6, "d6", [S12, S13]>;
71 def D7 : ARMReg< 7, "d7", [S14, S15]>;
72 def D8 : ARMReg< 8, "d8", [S16, S17]>;
73 def D9 : ARMReg< 9, "d9", [S18, S19]>;
74 def D10 : ARMReg<10, "d10", [S20, S21]>;
75 def D11 : ARMReg<11, "d11", [S22, S23]>;
76 def D12 : ARMReg<12, "d12", [S24, S25]>;
77 def D13 : ARMReg<13, "d13", [S26, S27]>;
78 def D14 : ARMReg<14, "d14", [S28, S29]>;
79 def D15 : ARMReg<15, "d15", [S30, S31]>;
81 // VFP3 defines 16 additional double registers
82 def D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d17">;
83 def D18 : ARMFReg<18, "d18">; def D19 : ARMFReg<19, "d19">;
84 def D20 : ARMFReg<20, "d20">; def D21 : ARMFReg<21, "d21">;
85 def D22 : ARMFReg<22, "d22">; def D23 : ARMFReg<23, "d23">;
86 def D24 : ARMFReg<24, "d24">; def D25 : ARMFReg<25, "d25">;
87 def D26 : ARMFReg<26, "d26">; def D27 : ARMFReg<27, "d27">;
88 def D28 : ARMFReg<28, "d28">; def D29 : ARMFReg<29, "d29">;
89 def D30 : ARMFReg<30, "d30">; def D31 : ARMFReg<31, "d31">;
90 def DDummy : ARMFReg<31, "dINVALID">;
92 // Advanced SIMD (NEON) defines 16 quad-word aliases
93 def Q0 : ARMReg< 0, "q0", [D0, D1]>;
94 def Q1 : ARMReg< 1, "q1", [D2, D3]>;
95 def Q2 : ARMReg< 2, "q2", [D4, D5]>;
96 def Q3 : ARMReg< 3, "q3", [D6, D7]>;
97 def Q4 : ARMReg< 4, "q4", [D8, D9]>;
98 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
99 def Q6 : ARMReg< 6, "q6", [D12, D13]>;
100 def Q7 : ARMReg< 7, "q7", [D14, D15]>;
101 def Q8 : ARMReg< 8, "q8", [D16, D17]>;
102 def Q9 : ARMReg< 9, "q9", [D18, D19]>;
103 def Q10 : ARMReg<10, "q10", [D20, D21]>;
104 def Q11 : ARMReg<11, "q11", [D22, D23]>;
105 def Q12 : ARMReg<12, "q12", [D24, D25]>;
106 def Q13 : ARMReg<13, "q13", [D26, D27]>;
107 def Q14 : ARMReg<14, "q14", [D28, D29]>;
108 def Q15 : ARMReg<15, "q15", [D30, D31]>;
109 def QDummy : ARMFReg<16, "qINVALID">;
111 // Pseudo 256-bit registers to represent pairs of Q registers. These should
112 // never be present in the emitted code.
113 // These are used for NEON load / store instructions, e.g. vld4, vst3.
114 // NOTE: It's possible to define more QQ registers since technical the
115 // starting D register number doesn't have to be multiple of 4. e.g.
116 // D1, D2, D3, D4 would be a legal quad. But that would make the sub-register
117 // stuffs very messy.
118 def QQ0 : ARMReg<0, "qq0", [Q0, Q1]>;
119 def QQ1 : ARMReg<1, "qq1", [Q2, Q3]>;
120 def QQ2 : ARMReg<2, "qq2", [Q4, Q5]>;
121 def QQ3 : ARMReg<3, "qq3", [Q6, Q7]>;
122 def QQ4 : ARMReg<4, "qq4", [Q8, Q9]>;
123 def QQ5 : ARMReg<5, "qq5", [Q10, Q11]>;
124 def QQ6 : ARMReg<6, "qq6", [Q12, Q13]>;
125 def QQ7 : ARMReg<7, "qq7", [Q14, Q15]>;
127 // Pseudo 512-bit registers to represent four consecutive Q registers.
128 def QQQQ0 : ARMReg<0, "qqqq0", [QQ0, QQ1]>;
129 def QQQQ1 : ARMReg<1, "qqqq1", [QQ2, QQ3]>;
130 def QQQQ2 : ARMReg<2, "qqqq2", [QQ4, QQ5]>;
131 def QQQQ3 : ARMReg<3, "qqqq3", [QQ6, QQ7]>;
133 // Current Program Status Register.
134 def CPSR : ARMReg<0, "cpsr">;
136 def FPSCR : ARMReg<1, "fpscr">;
140 // pc == Program Counter
141 // lr == Link Register
142 // sp == Stack Pointer
143 // r12 == ip (scratch)
144 // r7 == Frame Pointer (thumb-style backtraces)
145 // r9 == May be reserved as Thread Register
146 // r11 == Frame Pointer (arm-style backtraces)
147 // r10 == Stack Limit
149 def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
150 R7, R8, R9, R10, R11, R12,
152 let MethodProtos = [{
153 iterator allocation_order_begin(const MachineFunction &MF) const;
154 iterator allocation_order_end(const MachineFunction &MF) const;
156 let MethodBodies = [{
157 // FP is R11, R9 is available.
158 static const unsigned ARM_GPR_AO_1[] = {
159 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
161 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
162 ARM::R8, ARM::R9, ARM::R10,
164 // FP is R11, R9 is not available.
165 static const unsigned ARM_GPR_AO_2[] = {
166 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
168 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
171 // FP is R7, R9 is available as non-callee-saved register.
172 // This is used by Darwin.
173 static const unsigned ARM_GPR_AO_3[] = {
174 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
175 ARM::R9, ARM::R12,ARM::LR,
176 ARM::R4, ARM::R5, ARM::R6,
177 ARM::R8, ARM::R10,ARM::R11,ARM::R7 };
178 // FP is R7, R9 is not available.
179 static const unsigned ARM_GPR_AO_4[] = {
180 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
182 ARM::R4, ARM::R5, ARM::R6,
183 ARM::R8, ARM::R10,ARM::R11,
185 // FP is R7, R9 is available as callee-saved register.
186 // This is used by non-Darwin platform in Thumb mode.
187 static const unsigned ARM_GPR_AO_5[] = {
188 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
190 ARM::R4, ARM::R5, ARM::R6,
191 ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
193 // For Thumb1 mode, we don't want to allocate hi regs at all, as we
194 // don't know how to spill them. If we make our prologue/epilogue code
195 // smarter at some point, we can go back to using the above allocation
196 // orders for the Thumb1 instructions that know how to use hi regs.
197 static const unsigned THUMB_GPR_AO[] = {
198 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
199 ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
202 GPRClass::allocation_order_begin(const MachineFunction &MF) const {
203 const TargetMachine &TM = MF.getTarget();
204 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
205 if (Subtarget.isThumb1Only())
207 if (Subtarget.isTargetDarwin()) {
208 if (Subtarget.isR9Reserved())
213 if (Subtarget.isR9Reserved())
215 else if (Subtarget.isThumb())
223 GPRClass::allocation_order_end(const MachineFunction &MF) const {
224 const TargetMachine &TM = MF.getTarget();
225 const TargetRegisterInfo *RI = TM.getRegisterInfo();
226 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
227 GPRClass::iterator I;
229 if (Subtarget.isThumb1Only()) {
230 I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
231 // Mac OS X requires FP not to be clobbered for backtracing purpose.
232 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
235 if (Subtarget.isTargetDarwin()) {
236 if (Subtarget.isR9Reserved())
237 I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
239 I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
241 if (Subtarget.isR9Reserved())
242 I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
243 else if (Subtarget.isThumb())
244 I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
246 I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
249 // Mac OS X requires FP not to be clobbered for backtracing purpose.
250 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
255 // Thumb registers are R0-R7 normally. Some instructions can still use
256 // the general GPR register class above (MOV, e.g.)
257 def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
258 let MethodProtos = [{
259 iterator allocation_order_begin(const MachineFunction &MF) const;
260 iterator allocation_order_end(const MachineFunction &MF) const;
262 let MethodBodies = [{
263 static const unsigned THUMB_tGPR_AO[] = {
264 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
265 ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
267 // FP is R7, only low registers available.
269 tGPRClass::allocation_order_begin(const MachineFunction &MF) const {
270 return THUMB_tGPR_AO;
274 tGPRClass::allocation_order_end(const MachineFunction &MF) const {
275 const TargetMachine &TM = MF.getTarget();
276 const TargetRegisterInfo *RI = TM.getRegisterInfo();
277 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
278 tGPRClass::iterator I =
279 THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned));
280 // Mac OS X requires FP not to be clobbered for backtracing purpose.
281 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
286 // Scalar single precision floating point register class..
287 def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
288 S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
289 S23, S24, S25, S26, S27, S28, S29, S30, S31]>;
291 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
293 def SPR_8 : RegisterClass<"ARM", [f32], 32,
294 [S0, S1, S2, S3, S4, S5, S6, S7,
295 S8, S9, S10, S11, S12, S13, S14, S15]>;
297 // Dummy f32 regclass to represent impossible subreg indices.
298 def SPR_INVALID : RegisterClass<"ARM", [f32], 32, [SDummy]> {
302 // Scalar double precision floating point / generic 64-bit vector register
304 // ARM requires only word alignment for double. It's more performant if it
305 // is double-word alignment though.
306 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
307 [D0, D1, D2, D3, D4, D5, D6, D7,
308 D8, D9, D10, D11, D12, D13, D14, D15,
309 D16, D17, D18, D19, D20, D21, D22, D23,
310 D24, D25, D26, D27, D28, D29, D30, D31]> {
311 let SubRegClassList = [SPR_INVALID, SPR_INVALID];
312 let MethodProtos = [{
313 iterator allocation_order_begin(const MachineFunction &MF) const;
314 iterator allocation_order_end(const MachineFunction &MF) const;
316 let MethodBodies = [{
318 static const unsigned ARM_DPR_VFP2[] = {
319 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
320 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
321 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
322 ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
324 static const unsigned ARM_DPR_VFP3[] = {
325 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
326 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
327 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
328 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
329 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
330 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
331 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
332 ARM::D28, ARM::D29, ARM::D30, ARM::D31 };
334 DPRClass::allocation_order_begin(const MachineFunction &MF) const {
335 const TargetMachine &TM = MF.getTarget();
336 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
337 if (Subtarget.hasVFP3())
343 DPRClass::allocation_order_end(const MachineFunction &MF) const {
344 const TargetMachine &TM = MF.getTarget();
345 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
346 if (Subtarget.hasVFP3())
347 return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned));
349 return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned));
354 // Subset of DPR that are accessible with VFP2 (and so that also have
355 // 32-bit SPR subregs).
356 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
357 [D0, D1, D2, D3, D4, D5, D6, D7,
358 D8, D9, D10, D11, D12, D13, D14, D15]> {
359 let SubRegClassList = [SPR, SPR];
362 // Subset of DPR which can be used as a source of NEON scalars for 16-bit
364 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
365 [D0, D1, D2, D3, D4, D5, D6, D7]> {
366 let SubRegClassList = [SPR_8, SPR_8];
369 // Dummy 64-bit regclass to represent impossible subreg indices.
370 def DPR_INVALID : RegisterClass<"ARM",
371 [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
376 // Generic 128-bit vector register class.
377 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
378 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
379 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> {
380 let SubRegClassList = [SPR_INVALID, SPR_INVALID, SPR_INVALID, SPR_INVALID,
381 DPR, DPR, DPR_INVALID, DPR_INVALID,
382 DPR_INVALID, DPR_INVALID, DPR_INVALID, DPR_INVALID];
385 // Subset of QPR that have 32-bit SPR subregs.
386 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
388 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]> {
389 let SubRegClassList = [SPR, SPR, SPR, SPR,
390 DPR_VFP2, DPR_VFP2, DPR_INVALID, DPR_INVALID,
391 DPR_INVALID, DPR_INVALID, DPR_INVALID, DPR_INVALID];
394 // Subset of QPR that have DPR_8 and SPR_8 subregs.
395 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
398 let SubRegClassList = [SPR_8, SPR_8, SPR_8, SPR_8,
399 DPR_8, DPR_8, DPR_INVALID, DPR_INVALID,
400 DPR_INVALID, DPR_INVALID, DPR_INVALID, DPR_INVALID];
403 // Dummy 128-bit regclass to represent impossible subreg indices.
404 def QPR_INVALID : RegisterClass<"ARM",
405 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
410 // Pseudo 256-bit vector register class to model pairs of Q registers
411 // (4 consecutive D registers).
412 def QQPR : RegisterClass<"ARM", [v4i64],
414 [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7]> {
415 let SubRegClassList = [SPR_INVALID, SPR_INVALID, SPR_INVALID, SPR_INVALID,
417 DPR_INVALID, DPR_INVALID, DPR_INVALID, DPR_INVALID,
418 QPR, QPR, QPR_INVALID, QPR_INVALID];
421 // Subset of QQPR that have 32-bit SPR subregs.
422 def QQPR_VFP2 : RegisterClass<"ARM", [v4i64],
424 [QQ0, QQ1, QQ2, QQ3]> {
425 let SubRegClassList = [SPR, SPR, SPR, SPR,
426 DPR_VFP2, DPR_VFP2, DPR_VFP2, DPR_VFP2,
427 DPR_INVALID, DPR_INVALID, DPR_INVALID, DPR_INVALID,
428 QPR_VFP2, QPR_VFP2, QPR_INVALID, QPR_INVALID];
431 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
432 // (8 consecutive D registers).
433 def QQQQPR : RegisterClass<"ARM", [v8i64],
435 [QQQQ0, QQQQ1, QQQQ2, QQQQ3]> {
436 let SubRegClassList = [SPR_INVALID, SPR_INVALID, SPR_INVALID, SPR_INVALID,
437 DPR, DPR, DPR, DPR, DPR, DPR, DPR, DPR,
441 // Condition code registers.
442 def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
444 //===----------------------------------------------------------------------===//
445 // Subregister Set Definitions... now that we have all of the pieces, define the
446 // sub registers for each register.
449 def arm_ssubreg_0 : PatLeaf<(i32 1)>;
450 def arm_ssubreg_1 : PatLeaf<(i32 2)>;
451 def arm_ssubreg_2 : PatLeaf<(i32 3)>;
452 def arm_ssubreg_3 : PatLeaf<(i32 4)>;
454 def arm_dsubreg_0 : PatLeaf<(i32 5)>;
455 def arm_dsubreg_1 : PatLeaf<(i32 6)>;
456 def arm_dsubreg_2 : PatLeaf<(i32 7)>;
457 def arm_dsubreg_3 : PatLeaf<(i32 8)>;
458 def arm_dsubreg_4 : PatLeaf<(i32 9)>;
459 def arm_dsubreg_5 : PatLeaf<(i32 10)>;
460 def arm_dsubreg_6 : PatLeaf<(i32 11)>;
461 def arm_dsubreg_7 : PatLeaf<(i32 12)>;
463 def arm_qsubreg_0 : PatLeaf<(i32 13)>;
464 def arm_qsubreg_1 : PatLeaf<(i32 14)>;
465 def arm_qsubreg_2 : PatLeaf<(i32 15)>;
466 def arm_qsubreg_3 : PatLeaf<(i32 16)>;
468 def arm_qqsubreg_0 : PatLeaf<(i32 17)>;
469 def arm_qqsubreg_1 : PatLeaf<(i32 18)>;
472 // S sub-registers of D registers.
473 def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
474 D8, D9, D10, D11, D12, D13, D14, D15],
475 [S0, S2, S4, S6, S8, S10, S12, S14,
476 S16, S18, S20, S22, S24, S26, S28, S30]>;
477 def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
478 D8, D9, D10, D11, D12, D13, D14, D15],
479 [S1, S3, S5, S7, S9, S11, S13, S15,
480 S17, S19, S21, S23, S25, S27, S29, S31]>;
482 // S sub-registers of Q registers.
483 def : SubRegSet<1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
484 [S0, S4, S8, S12, S16, S20, S24, S28]>;
485 def : SubRegSet<2, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
486 [S1, S5, S9, S13, S17, S21, S25, S29]>;
487 def : SubRegSet<3, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
488 [S2, S6, S10, S14, S18, S22, S26, S30]>;
489 def : SubRegSet<4, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
490 [S3, S7, S11, S15, S19, S23, S27, S31]>;
492 // D sub-registers of Q registers.
493 def : SubRegSet<5, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
494 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
495 [D0, D2, D4, D6, D8, D10, D12, D14,
496 D16, D18, D20, D22, D24, D26, D28, D30]>;
497 def : SubRegSet<6, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
498 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
499 [D1, D3, D5, D7, D9, D11, D13, D15,
500 D17, D19, D21, D23, D25, D27, D29, D31]>;
502 // S sub-registers of QQ registers. Note there are no sub-indices
503 // for referencing S4 - S7, S12 - S15, and S20 - S23. It doesn't
504 // look like we need them.
505 def : SubRegSet<1, [QQ0, QQ1, QQ2, QQ3],
507 def : SubRegSet<2, [QQ0, QQ1, QQ2, QQ3],
509 def : SubRegSet<3, [QQ0, QQ1, QQ2, QQ3],
510 [S2, S10, S18, S26]>;
511 def : SubRegSet<4, [QQ0, QQ1, QQ2, QQ3],
512 [S3, S11, S19, S27]>;
514 // D sub-registers of QQ registers.
515 def : SubRegSet<5, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
516 [D0, D4, D8, D12, D16, D20, D24, D28]>;
517 def : SubRegSet<6, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
518 [D1, D5, D9, D13, D17, D21, D25, D29]>;
519 def : SubRegSet<7, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
520 [D2, D6, D10, D14, D18, D22, D26, D30]>;
521 def : SubRegSet<8, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
522 [D3, D7, D11, D15, D19, D23, D27, D31]>;
524 // Q sub-registers of QQ registers.
525 def : SubRegSet<13, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
526 [Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14]>;
527 def : SubRegSet<14,[QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
528 [Q1, Q3, Q5, Q7, Q9, Q11, Q13, Q15]>;
531 // D sub-registers of QQQQ registers.
532 def : SubRegSet<5, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
534 def : SubRegSet<6, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
536 def : SubRegSet<7, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
537 [D2, D10, D18, D26]>;
538 def : SubRegSet<8, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
539 [D3, D11, D19, D27]>;
541 def : SubRegSet<9, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
542 [D4, D12, D20, D28]>;
543 def : SubRegSet<10, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
544 [D5, D13, D21, D29]>;
545 def : SubRegSet<11, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
546 [D6, D14, D22, D30]>;
547 def : SubRegSet<12, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
548 [D7, D15, D23, D31]>;
550 // Q sub-registers of QQQQQQQQ registers.
551 def : SubRegSet<13, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
553 def : SubRegSet<14, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
555 def : SubRegSet<15, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
557 def : SubRegSet<16, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
560 // QQ sub-registers of QQQQQQQQ registers.
561 def : SubRegSet<17, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
562 [QQ0, QQ2, QQ4, QQ6]>;
563 def : SubRegSet<18, [QQQQ0, QQQQ1, QQQQ2, QQQQ3],
564 [QQ1, QQ3, QQ5, QQ7]>;