1 //===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the ARM register file
12 //===----------------------------------------------------------------------===//
14 // Registers are identified with 4-bit ID numbers.
15 class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
17 let Namespace = "ARM";
18 let SubRegs = subregs;
19 // All bits of ARM registers with sub-registers are covered by sub-registers.
20 let CoveredBySubRegs = 1;
23 class ARMFReg<bits<6> num, string n> : Register<n> {
25 let Namespace = "ARM";
28 // Subregister indices.
29 let Namespace = "ARM" in {
30 def qqsub_0 : SubRegIndex;
31 def qqsub_1 : SubRegIndex;
33 // Note: Code depends on these having consecutive numbers.
34 def qsub_0 : SubRegIndex;
35 def qsub_1 : SubRegIndex;
36 def qsub_2 : SubRegIndex<[qqsub_1, qsub_0]>;
37 def qsub_3 : SubRegIndex<[qqsub_1, qsub_1]>;
39 def dsub_0 : SubRegIndex;
40 def dsub_1 : SubRegIndex;
41 def dsub_2 : SubRegIndex<[qsub_1, dsub_0]>;
42 def dsub_3 : SubRegIndex<[qsub_1, dsub_1]>;
43 def dsub_4 : SubRegIndex<[qsub_2, dsub_0]>;
44 def dsub_5 : SubRegIndex<[qsub_2, dsub_1]>;
45 def dsub_6 : SubRegIndex<[qsub_3, dsub_0]>;
46 def dsub_7 : SubRegIndex<[qsub_3, dsub_1]>;
48 def ssub_0 : SubRegIndex;
49 def ssub_1 : SubRegIndex;
50 def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
51 def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;
52 // Let TableGen synthesize the remaining 12 ssub_* indices.
53 // We don't need to name them.
57 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
58 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
59 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
60 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
61 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
62 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
63 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
64 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
65 // These require 32-bit instructions.
66 let CostPerUse = 1 in {
67 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
68 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
69 def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
70 def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
71 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
72 def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
73 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
74 def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
78 def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
79 def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">;
80 def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">;
81 def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">;
82 def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">;
83 def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
84 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
85 def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
86 def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
87 def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
88 def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
89 def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
90 def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
91 def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
92 def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
93 def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
95 // Aliases of the F* registers used to hold 64-bit fp values (doubles)
96 let SubRegIndices = [ssub_0, ssub_1] in {
97 def D0 : ARMReg< 0, "d0", [S0, S1]>, DwarfRegNum<[256]>;
98 def D1 : ARMReg< 1, "d1", [S2, S3]>, DwarfRegNum<[257]>;
99 def D2 : ARMReg< 2, "d2", [S4, S5]>, DwarfRegNum<[258]>;
100 def D3 : ARMReg< 3, "d3", [S6, S7]>, DwarfRegNum<[259]>;
101 def D4 : ARMReg< 4, "d4", [S8, S9]>, DwarfRegNum<[260]>;
102 def D5 : ARMReg< 5, "d5", [S10, S11]>, DwarfRegNum<[261]>;
103 def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>;
104 def D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>;
105 def D8 : ARMReg< 8, "d8", [S16, S17]>, DwarfRegNum<[264]>;
106 def D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>;
107 def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
108 def D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>;
109 def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>;
110 def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>;
111 def D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>;
112 def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>;
115 // VFP3 defines 16 additional double registers
116 def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>;
117 def D17 : ARMFReg<17, "d17">, DwarfRegNum<[273]>;
118 def D18 : ARMFReg<18, "d18">, DwarfRegNum<[274]>;
119 def D19 : ARMFReg<19, "d19">, DwarfRegNum<[275]>;
120 def D20 : ARMFReg<20, "d20">, DwarfRegNum<[276]>;
121 def D21 : ARMFReg<21, "d21">, DwarfRegNum<[277]>;
122 def D22 : ARMFReg<22, "d22">, DwarfRegNum<[278]>;
123 def D23 : ARMFReg<23, "d23">, DwarfRegNum<[279]>;
124 def D24 : ARMFReg<24, "d24">, DwarfRegNum<[280]>;
125 def D25 : ARMFReg<25, "d25">, DwarfRegNum<[281]>;
126 def D26 : ARMFReg<26, "d26">, DwarfRegNum<[282]>;
127 def D27 : ARMFReg<27, "d27">, DwarfRegNum<[283]>;
128 def D28 : ARMFReg<28, "d28">, DwarfRegNum<[284]>;
129 def D29 : ARMFReg<29, "d29">, DwarfRegNum<[285]>;
130 def D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>;
131 def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;
133 // Advanced SIMD (NEON) defines 16 quad-word aliases
134 let SubRegIndices = [dsub_0, dsub_1] in {
135 def Q0 : ARMReg< 0, "q0", [D0, D1]>;
136 def Q1 : ARMReg< 1, "q1", [D2, D3]>;
137 def Q2 : ARMReg< 2, "q2", [D4, D5]>;
138 def Q3 : ARMReg< 3, "q3", [D6, D7]>;
139 def Q4 : ARMReg< 4, "q4", [D8, D9]>;
140 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
141 def Q6 : ARMReg< 6, "q6", [D12, D13]>;
142 def Q7 : ARMReg< 7, "q7", [D14, D15]>;
144 let SubRegIndices = [dsub_0, dsub_1] in {
145 def Q8 : ARMReg< 8, "q8", [D16, D17]>;
146 def Q9 : ARMReg< 9, "q9", [D18, D19]>;
147 def Q10 : ARMReg<10, "q10", [D20, D21]>;
148 def Q11 : ARMReg<11, "q11", [D22, D23]>;
149 def Q12 : ARMReg<12, "q12", [D24, D25]>;
150 def Q13 : ARMReg<13, "q13", [D26, D27]>;
151 def Q14 : ARMReg<14, "q14", [D28, D29]>;
152 def Q15 : ARMReg<15, "q15", [D30, D31]>;
155 // Current Program Status Register.
156 // We model fpscr with two registers: FPSCR models the control bits and will be
157 // reserved. FPSCR_NZCV models the flag bits and will be unreserved.
158 def CPSR : ARMReg<0, "cpsr">;
159 def APSR : ARMReg<1, "apsr">;
160 def SPSR : ARMReg<2, "spsr">;
161 def FPSCR : ARMReg<3, "fpscr">;
162 def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> {
163 let Aliases = [FPSCR];
165 def ITSTATE : ARMReg<4, "itstate">;
167 // Special Registers - only available in privileged mode.
168 def FPSID : ARMReg<0, "fpsid">;
169 def FPEXC : ARMReg<8, "fpexc">;
173 // pc == Program Counter
174 // lr == Link Register
175 // sp == Stack Pointer
176 // r12 == ip (scratch)
177 // r7 == Frame Pointer (thumb-style backtraces)
178 // r9 == May be reserved as Thread Register
179 // r11 == Frame Pointer (arm-style backtraces)
180 // r10 == Stack Limit
182 def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
184 // Allocate LR as the first CSR since it is always saved anyway.
185 // For Thumb1 mode, we don't want to allocate hi regs at all, as we don't
186 // know how to spill them. If we make our prologue/epilogue code smarter at
187 // some point, we can go back to using the above allocation orders for the
188 // Thumb1 instructions that know how to use hi regs.
189 let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
190 let AltOrderSelect = [{
191 return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
195 // GPRs without the PC. Some ARM instructions do not allow the PC in
196 // certain operand slots, particularly as the destination. Primarily
197 // useful for disassembly.
198 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
199 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
200 let AltOrderSelect = [{
201 return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
205 // GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the
206 // implied SP argument list.
207 // FIXME: It would be better to not use this at all and refactor the
208 // instructions to not have SP an an explicit argument. That makes
209 // frame index resolution a bit trickier, though.
210 def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>;
212 // restricted GPR register class. Many Thumb2 instructions allow the full
213 // register range for operands, but have undefined behaviours when PC
214 // or SP (R13 or R15) are used. The ARM ISA refers to these operands
215 // via the BadReg() pseudo-code description.
216 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
217 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
218 let AltOrderSelect = [{
219 return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
223 // Thumb registers are R0-R7 normally. Some instructions can still use
224 // the general GPR register class above (MOV, e.g.)
225 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
227 // The high registers in thumb mode, R8-R15.
228 def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
230 // For tail calls, we can't use callee-saved registers, as they are restored
231 // to the saved value before the tail call, which would clobber a call address.
232 // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of
233 // this class and the preceding one(!) This is what we want.
234 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> {
235 let AltOrders = [(and tcGPR, tGPR)];
236 let AltOrderSelect = [{
237 return MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
241 // Condition code registers.
242 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
243 let CopyCost = -1; // Don't allow copying of status registers.
244 let isAllocatable = 0;
247 // Scalar single precision floating point register class..
248 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)>;
250 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
252 def SPR_8 : RegisterClass<"ARM", [f32], 32, (trunc SPR, 16)>;
254 // Scalar double precision floating point / generic 64-bit vector register
256 // ARM requires only word alignment for double. It's more performant if it
257 // is double-word alignment though.
258 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
259 (sequence "D%u", 0, 31)> {
260 // Allocate non-VFP2 registers D16-D31 first.
261 let AltOrders = [(rotl DPR, 16)];
262 let AltOrderSelect = [{ return 1; }];
265 // Subset of DPR that are accessible with VFP2 (and so that also have
266 // 32-bit SPR subregs).
267 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
269 let SubRegClasses = [(SPR ssub_0, ssub_1)];
272 // Subset of DPR which can be used as a source of NEON scalars for 16-bit
274 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
276 let SubRegClasses = [(SPR_8 ssub_0, ssub_1)];
279 // Generic 128-bit vector register class.
280 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
281 (sequence "Q%u", 0, 15)> {
282 let SubRegClasses = [(DPR dsub_0, dsub_1)];
283 // Allocate non-VFP2 aliases Q8-Q15 first.
284 let AltOrders = [(rotl QPR, 8)];
285 let AltOrderSelect = [{ return 1; }];
288 // Subset of QPR that have 32-bit SPR subregs.
289 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
290 128, (trunc QPR, 8)> {
291 let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
292 (DPR_VFP2 dsub_0, dsub_1)];
295 // Subset of QPR that have DPR_8 and SPR_8 subregs.
296 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
297 128, (trunc QPR, 4)> {
298 let SubRegClasses = [(SPR_8 ssub_0, ssub_1, ssub_2, ssub_3),
299 (DPR_8 dsub_0, dsub_1)];
302 // Pseudo-registers representing odd-even pairs of D registers. The even-odd
303 // pairs are already represented by the Q registers.
304 // These are needed by NEON instructions requiring two consecutive D registers.
305 // There is no D31_D0 register as that is always an UNPREDICTABLE encoding.
306 def TuplesOE2D : RegisterTuples<[dsub_0, dsub_1],
307 [(decimate (shl DPR, 1), 2),
308 (decimate (shl DPR, 2), 2)]>;
310 // Register class representing a pair of consecutive D registers.
311 // Use the Q registers for the even-odd pairs.
312 def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
313 128, (interleave QPR, TuplesOE2D)> {
314 // Allocate starting at non-VFP2 registers D16-D31 first.
315 let AltOrders = [(rotl DPair, 16)];
316 let AltOrderSelect = [{ return 1; }];
319 // Pseudo-registers representing 3 consecutive D registers.
320 def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2],
325 // 3 consecutive D registers.
326 def DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> {
327 let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
330 // Pseudo 256-bit registers to represent pairs of Q registers. These should
331 // never be present in the emitted code.
332 // These are used for NEON load / store instructions, e.g., vld4, vst3.
333 def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>;
335 // Pseudo 256-bit vector register class to model pairs of Q registers
336 // (4 consecutive D registers).
337 def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> {
338 let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3),
339 (QPR qsub_0, qsub_1)];
340 // Allocate non-VFP2 aliases first.
341 let AltOrders = [(rotl QQPR, 8)];
342 let AltOrderSelect = [{ return 1; }];
345 // Tuples of 4 D regs that isn't also a pair of Q regs.
346 def TuplesOE4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3],
347 [(decimate (shl DPR, 1), 2),
348 (decimate (shl DPR, 2), 2),
349 (decimate (shl DPR, 3), 2),
350 (decimate (shl DPR, 4), 2)]>;
352 // 4 consecutive D registers.
353 def DQuad : RegisterClass<"ARM", [v4i64], 256,
354 (interleave Tuples2Q, TuplesOE4D)>;
356 // Pseudo 512-bit registers to represent four consecutive Q registers.
357 def Tuples2QQ : RegisterTuples<[qqsub_0, qqsub_1],
358 [(shl QQPR, 0), (shl QQPR, 2)]>;
360 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
361 // (8 consecutive D registers).
362 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
363 let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3,
364 dsub_4, dsub_5, dsub_6, dsub_7),
365 (QPR qsub_0, qsub_1, qsub_2, qsub_3)];
366 // Allocate non-VFP2 aliases first.
367 let AltOrders = [(rotl QQQQPR, 8)];
368 let AltOrderSelect = [{ return 1; }];
372 // Pseudo-registers representing 2-spaced consecutive D registers.
373 def Tuples2DSpc : RegisterTuples<[dsub_0, dsub_2],
377 // Spaced pairs of D registers.
378 def DPairSpc : RegisterClass<"ARM", [v2i64], 64, (add Tuples2DSpc)>;
380 def Tuples3DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4],
385 // Spaced triples of D registers.
386 def DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> {
387 let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
390 def Tuples4DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4, dsub_6],
396 // Spaced quads of D registers.
397 def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>;