1 //===- ARMRegisterInfo.td - ARM Register defs --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the ARM register file
12 //===----------------------------------------------------------------------===//
14 // Registers are identified with 4-bit ID numbers.
15 class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
17 let Namespace = "ARM";
18 let SubRegs = subregs;
21 class ARMFReg<bits<6> num, string n> : Register<n> {
23 let Namespace = "ARM";
26 // Subregister indices.
27 let Namespace = "ARM" in {
28 // Note: Code depends on these having consecutive numbers.
29 def ssub_0 : SubRegIndex;
30 def ssub_1 : SubRegIndex;
31 def ssub_2 : SubRegIndex; // In a Q reg.
32 def ssub_3 : SubRegIndex;
33 def ssub_4 : SubRegIndex; // In a QQ reg.
34 def ssub_5 : SubRegIndex;
35 def ssub_6 : SubRegIndex;
36 def ssub_7 : SubRegIndex;
37 def ssub_8 : SubRegIndex; // In a QQQQ reg.
38 def ssub_9 : SubRegIndex;
39 def ssub_10 : SubRegIndex;
40 def ssub_11 : SubRegIndex;
41 def ssub_12 : SubRegIndex;
42 def ssub_13 : SubRegIndex;
43 def ssub_14 : SubRegIndex;
44 def ssub_15 : SubRegIndex;
46 def dsub_0 : SubRegIndex;
47 def dsub_1 : SubRegIndex;
48 def dsub_2 : SubRegIndex;
49 def dsub_3 : SubRegIndex;
50 def dsub_4 : SubRegIndex;
51 def dsub_5 : SubRegIndex;
52 def dsub_6 : SubRegIndex;
53 def dsub_7 : SubRegIndex;
55 def qsub_0 : SubRegIndex;
56 def qsub_1 : SubRegIndex;
57 def qsub_2 : SubRegIndex;
58 def qsub_3 : SubRegIndex;
60 def qqsub_0 : SubRegIndex;
61 def qqsub_1 : SubRegIndex;
65 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
66 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
67 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
68 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
69 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
70 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
71 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
72 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
73 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
74 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
75 def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
76 def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
77 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
78 def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
79 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
80 def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
83 def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
84 def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">;
85 def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">;
86 def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">;
87 def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">;
88 def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
89 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
90 def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
91 def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
92 def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
93 def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
94 def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
95 def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
96 def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
97 def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
98 def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
100 // Aliases of the F* registers used to hold 64-bit fp values (doubles)
101 let SubRegIndices = [ssub_0, ssub_1] in {
102 def D0 : ARMReg< 0, "d0", [S0, S1]>;
103 def D1 : ARMReg< 1, "d1", [S2, S3]>;
104 def D2 : ARMReg< 2, "d2", [S4, S5]>;
105 def D3 : ARMReg< 3, "d3", [S6, S7]>;
106 def D4 : ARMReg< 4, "d4", [S8, S9]>;
107 def D5 : ARMReg< 5, "d5", [S10, S11]>;
108 def D6 : ARMReg< 6, "d6", [S12, S13]>;
109 def D7 : ARMReg< 7, "d7", [S14, S15]>;
110 def D8 : ARMReg< 8, "d8", [S16, S17]>;
111 def D9 : ARMReg< 9, "d9", [S18, S19]>;
112 def D10 : ARMReg<10, "d10", [S20, S21]>;
113 def D11 : ARMReg<11, "d11", [S22, S23]>;
114 def D12 : ARMReg<12, "d12", [S24, S25]>;
115 def D13 : ARMReg<13, "d13", [S26, S27]>;
116 def D14 : ARMReg<14, "d14", [S28, S29]>;
117 def D15 : ARMReg<15, "d15", [S30, S31]>;
120 // VFP3 defines 16 additional double registers
121 def D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d17">;
122 def D18 : ARMFReg<18, "d18">; def D19 : ARMFReg<19, "d19">;
123 def D20 : ARMFReg<20, "d20">; def D21 : ARMFReg<21, "d21">;
124 def D22 : ARMFReg<22, "d22">; def D23 : ARMFReg<23, "d23">;
125 def D24 : ARMFReg<24, "d24">; def D25 : ARMFReg<25, "d25">;
126 def D26 : ARMFReg<26, "d26">; def D27 : ARMFReg<27, "d27">;
127 def D28 : ARMFReg<28, "d28">; def D29 : ARMFReg<29, "d29">;
128 def D30 : ARMFReg<30, "d30">; def D31 : ARMFReg<31, "d31">;
130 // Advanced SIMD (NEON) defines 16 quad-word aliases
131 let SubRegIndices = [dsub_0, dsub_1],
132 CompositeIndices = [(ssub_2 dsub_1, ssub_0),
133 (ssub_3 dsub_1, ssub_1)] in {
134 def Q0 : ARMReg< 0, "q0", [D0, D1]>;
135 def Q1 : ARMReg< 1, "q1", [D2, D3]>;
136 def Q2 : ARMReg< 2, "q2", [D4, D5]>;
137 def Q3 : ARMReg< 3, "q3", [D6, D7]>;
138 def Q4 : ARMReg< 4, "q4", [D8, D9]>;
139 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
140 def Q6 : ARMReg< 6, "q6", [D12, D13]>;
141 def Q7 : ARMReg< 7, "q7", [D14, D15]>;
143 let SubRegIndices = [dsub_0, dsub_1] in {
144 def Q8 : ARMReg< 8, "q8", [D16, D17]>;
145 def Q9 : ARMReg< 9, "q9", [D18, D19]>;
146 def Q10 : ARMReg<10, "q10", [D20, D21]>;
147 def Q11 : ARMReg<11, "q11", [D22, D23]>;
148 def Q12 : ARMReg<12, "q12", [D24, D25]>;
149 def Q13 : ARMReg<13, "q13", [D26, D27]>;
150 def Q14 : ARMReg<14, "q14", [D28, D29]>;
151 def Q15 : ARMReg<15, "q15", [D30, D31]>;
154 // Pseudo 256-bit registers to represent pairs of Q registers. These should
155 // never be present in the emitted code.
156 // These are used for NEON load / store instructions, e.g., vld4, vst3.
157 // NOTE: It's possible to define more QQ registers since technically the
158 // starting D register number doesn't have to be multiple of 4, e.g.,
159 // D1, D2, D3, D4 would be a legal quad, but that would make the subregister
161 let SubRegIndices = [qsub_0, qsub_1] in {
162 let CompositeIndices = [(dsub_2 qsub_1, dsub_0), (dsub_3 qsub_1, dsub_1),
163 (ssub_4 qsub_1, ssub_0), (ssub_5 qsub_1, ssub_1),
164 (ssub_6 qsub_1, ssub_2), (ssub_7 qsub_1, ssub_3)] in {
165 def QQ0 : ARMReg<0, "qq0", [Q0, Q1]>;
166 def QQ1 : ARMReg<1, "qq1", [Q2, Q3]>;
167 def QQ2 : ARMReg<2, "qq2", [Q4, Q5]>;
168 def QQ3 : ARMReg<3, "qq3", [Q6, Q7]>;
170 let CompositeIndices = [(dsub_2 qsub_1, dsub_0), (dsub_3 qsub_1, dsub_1)] in {
171 def QQ4 : ARMReg<4, "qq4", [Q8, Q9]>;
172 def QQ5 : ARMReg<5, "qq5", [Q10, Q11]>;
173 def QQ6 : ARMReg<6, "qq6", [Q12, Q13]>;
174 def QQ7 : ARMReg<7, "qq7", [Q14, Q15]>;
178 // Pseudo 512-bit registers to represent four consecutive Q registers.
179 let SubRegIndices = [qqsub_0, qqsub_1] in {
180 let CompositeIndices = [(qsub_2 qqsub_1, qsub_0), (qsub_3 qqsub_1, qsub_1),
181 (dsub_4 qqsub_1, dsub_0), (dsub_5 qqsub_1, dsub_1),
182 (dsub_6 qqsub_1, dsub_2), (dsub_7 qqsub_1, dsub_3),
183 (ssub_8 qqsub_1, ssub_0), (ssub_9 qqsub_1, ssub_1),
184 (ssub_10 qqsub_1, ssub_2), (ssub_11 qqsub_1, ssub_3),
185 (ssub_12 qqsub_1, ssub_4), (ssub_13 qqsub_1, ssub_5),
186 (ssub_14 qqsub_1, ssub_6), (ssub_15 qqsub_1, ssub_7)] in
188 def QQQQ0 : ARMReg<0, "qqqq0", [QQ0, QQ1]>;
189 def QQQQ1 : ARMReg<1, "qqqq1", [QQ2, QQ3]>;
191 let CompositeIndices = [(qsub_2 qqsub_1, qsub_0), (qsub_3 qqsub_1, qsub_1),
192 (dsub_4 qqsub_1, dsub_0), (dsub_5 qqsub_1, dsub_1),
193 (dsub_6 qqsub_1, dsub_2), (dsub_7 qqsub_1, dsub_3)] in {
194 def QQQQ2 : ARMReg<2, "qqqq2", [QQ4, QQ5]>;
195 def QQQQ3 : ARMReg<3, "qqqq3", [QQ6, QQ7]>;
199 // Current Program Status Register.
200 def CPSR : ARMReg<0, "cpsr">;
201 def FPSCR : ARMReg<1, "fpscr">;
202 def ITSTATE : ARMReg<2, "itstate">;
206 // pc == Program Counter
207 // lr == Link Register
208 // sp == Stack Pointer
209 // r12 == ip (scratch)
210 // r7 == Frame Pointer (thumb-style backtraces)
211 // r9 == May be reserved as Thread Register
212 // r11 == Frame Pointer (arm-style backtraces)
213 // r10 == Stack Limit
215 def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
216 R7, R8, R9, R10, R11, R12,
218 let MethodProtos = [{
219 iterator allocation_order_begin(const MachineFunction &MF) const;
220 iterator allocation_order_end(const MachineFunction &MF) const;
222 let MethodBodies = [{
223 // FP is R11, R9 is available.
224 static const unsigned ARM_GPR_AO_1[] = {
225 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
227 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
228 ARM::R8, ARM::R9, ARM::R10,
230 // FP is R11, R9 is not available.
231 static const unsigned ARM_GPR_AO_2[] = {
232 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
234 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
237 // FP is R7, R9 is available as non-callee-saved register.
238 // This is used by Darwin.
239 static const unsigned ARM_GPR_AO_3[] = {
240 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
241 ARM::R9, ARM::R12,ARM::LR,
242 ARM::R4, ARM::R5, ARM::R6,
243 ARM::R8, ARM::R10,ARM::R11,ARM::R7 };
244 // FP is R7, R9 is not available.
245 static const unsigned ARM_GPR_AO_4[] = {
246 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
248 ARM::R4, ARM::R5, ARM::R6,
249 ARM::R8, ARM::R10,ARM::R11,
251 // FP is R7, R9 is available as callee-saved register.
252 // This is used by non-Darwin platform in Thumb mode.
253 static const unsigned ARM_GPR_AO_5[] = {
254 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
256 ARM::R4, ARM::R5, ARM::R6,
257 ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
259 // For Thumb1 mode, we don't want to allocate hi regs at all, as we
260 // don't know how to spill them. If we make our prologue/epilogue code
261 // smarter at some point, we can go back to using the above allocation
262 // orders for the Thumb1 instructions that know how to use hi regs.
263 static const unsigned THUMB_GPR_AO[] = {
264 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
265 ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
268 GPRClass::allocation_order_begin(const MachineFunction &MF) const {
269 const TargetMachine &TM = MF.getTarget();
270 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
271 if (Subtarget.isThumb1Only())
273 if (Subtarget.isTargetDarwin()) {
274 if (Subtarget.isR9Reserved())
279 if (Subtarget.isR9Reserved())
281 else if (Subtarget.isThumb())
289 GPRClass::allocation_order_end(const MachineFunction &MF) const {
290 const TargetMachine &TM = MF.getTarget();
291 const TargetRegisterInfo *RI = TM.getRegisterInfo();
292 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
293 GPRClass::iterator I;
295 if (Subtarget.isThumb1Only()) {
296 I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
297 return RI->hasFP(MF) ? I-1 : I;
300 if (Subtarget.isTargetDarwin()) {
301 if (Subtarget.isR9Reserved())
302 I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
304 I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
306 if (Subtarget.isR9Reserved())
307 I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
308 else if (Subtarget.isThumb())
309 I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
311 I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
314 return RI->hasFP(MF) ? I-1 : I;
319 // restricted GPR register class. Many Thumb2 instructions allow the full
320 // register range for operands, but have undefined behaviours when PC
321 // or SP (R13 or R15) are used. The ARM ARM refers to these operands
322 // via the BadReg() pseudo-code description.
323 def rGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
324 R7, R8, R9, R10, R11, R12, LR]> {
325 let MethodProtos = [{
326 iterator allocation_order_begin(const MachineFunction &MF) const;
327 iterator allocation_order_end(const MachineFunction &MF) const;
329 let MethodBodies = [{
330 // FP is R11, R9 is available.
331 static const unsigned ARM_rGPRAO_1[] = {
332 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
334 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
335 ARM::R8, ARM::R9, ARM::R10,
337 // FP is R11, R9 is not available.
338 static const unsigned ARM_rGPRAO_2[] = {
339 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
341 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
344 // FP is R7, R9 is available as non-callee-saved register.
345 // This is used by Darwin.
346 static const unsigned ARM_rGPRAO_3[] = {
347 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
348 ARM::R9, ARM::R12,ARM::LR,
349 ARM::R4, ARM::R5, ARM::R6,
350 ARM::R8, ARM::R10,ARM::R11,ARM::R7 };
351 // FP is R7, R9 is not available.
352 static const unsigned ARM_rGPRAO_4[] = {
353 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
355 ARM::R4, ARM::R5, ARM::R6,
356 ARM::R8, ARM::R10,ARM::R11,
358 // FP is R7, R9 is available as callee-saved register.
359 // This is used by non-Darwin platform in Thumb mode.
360 static const unsigned ARM_rGPRAO_5[] = {
361 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
363 ARM::R4, ARM::R5, ARM::R6,
364 ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
366 // For Thumb1 mode, we don't want to allocate hi regs at all, as we
367 // don't know how to spill them. If we make our prologue/epilogue code
368 // smarter at some point, we can go back to using the above allocation
369 // orders for the Thumb1 instructions that know how to use hi regs.
370 static const unsigned THUMB_rGPRAO[] = {
371 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
372 ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
375 rGPRClass::allocation_order_begin(const MachineFunction &MF) const {
376 const TargetMachine &TM = MF.getTarget();
377 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
378 if (Subtarget.isThumb1Only())
380 if (Subtarget.isTargetDarwin()) {
381 if (Subtarget.isR9Reserved())
386 if (Subtarget.isR9Reserved())
388 else if (Subtarget.isThumb())
396 rGPRClass::allocation_order_end(const MachineFunction &MF) const {
397 const TargetMachine &TM = MF.getTarget();
398 const TargetRegisterInfo *RI = TM.getRegisterInfo();
399 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
400 GPRClass::iterator I;
402 if (Subtarget.isThumb1Only()) {
403 I = THUMB_rGPRAO + (sizeof(THUMB_rGPRAO)/sizeof(unsigned));
404 return RI->hasFP(MF) ? I-1 : I;
407 if (Subtarget.isTargetDarwin()) {
408 if (Subtarget.isR9Reserved())
409 I = ARM_rGPRAO_4 + (sizeof(ARM_rGPRAO_4)/sizeof(unsigned));
411 I = ARM_rGPRAO_3 + (sizeof(ARM_rGPRAO_3)/sizeof(unsigned));
413 if (Subtarget.isR9Reserved())
414 I = ARM_rGPRAO_2 + (sizeof(ARM_rGPRAO_2)/sizeof(unsigned));
415 else if (Subtarget.isThumb())
416 I = ARM_rGPRAO_5 + (sizeof(ARM_rGPRAO_5)/sizeof(unsigned));
418 I = ARM_rGPRAO_1 + (sizeof(ARM_rGPRAO_1)/sizeof(unsigned));
421 return RI->hasFP(MF) ? I-1 : I;
426 // Thumb registers are R0-R7 normally. Some instructions can still use
427 // the general GPR register class above (MOV, e.g.)
428 def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {}
430 // For tail calls, we can't use callee-saved registers, as they are restored
431 // to the saved value before the tail call, which would clobber a call address.
432 // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of
433 // this class and the preceding one(!) This is what we want.
434 def tcGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R9, R12]> {
435 let MethodProtos = [{
436 iterator allocation_order_begin(const MachineFunction &MF) const;
437 iterator allocation_order_end(const MachineFunction &MF) const;
439 let MethodBodies = [{
441 static const unsigned ARM_GPR_R9_TC[] = {
442 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
444 // R9 is not available.
445 static const unsigned ARM_GPR_NOR9_TC[] = {
446 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
449 // For Thumb1 mode, we don't want to allocate hi regs at all, as we
450 // don't know how to spill them. If we make our prologue/epilogue code
451 // smarter at some point, we can go back to using the above allocation
452 // orders for the Thumb1 instructions that know how to use hi regs.
453 static const unsigned THUMB_GPR_AO_TC[] = {
454 ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
457 tcGPRClass::allocation_order_begin(const MachineFunction &MF) const {
458 const TargetMachine &TM = MF.getTarget();
459 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
460 if (Subtarget.isThumb1Only())
461 return THUMB_GPR_AO_TC;
462 if (Subtarget.isTargetDarwin()) {
463 if (Subtarget.isR9Reserved())
464 return ARM_GPR_NOR9_TC;
466 return ARM_GPR_R9_TC;
468 // R9 is either callee-saved or reserved; can't use it.
469 return ARM_GPR_NOR9_TC;
473 tcGPRClass::allocation_order_end(const MachineFunction &MF) const {
474 const TargetMachine &TM = MF.getTarget();
475 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
476 GPRClass::iterator I;
478 if (Subtarget.isThumb1Only()) {
479 I = THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned));
483 if (Subtarget.isTargetDarwin()) {
484 if (Subtarget.isR9Reserved())
485 I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned));
487 I = ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned));
489 // R9 is either callee-saved or reserved; can't use it.
490 I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned));
497 // Scalar single precision floating point register class..
498 def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
499 S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
500 S23, S24, S25, S26, S27, S28, S29, S30, S31]>;
502 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
504 def SPR_8 : RegisterClass<"ARM", [f32], 32,
505 [S0, S1, S2, S3, S4, S5, S6, S7,
506 S8, S9, S10, S11, S12, S13, S14, S15]>;
508 // Scalar double precision floating point / generic 64-bit vector register
510 // ARM requires only word alignment for double. It's more performant if it
511 // is double-word alignment though.
512 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
513 [D0, D1, D2, D3, D4, D5, D6, D7,
514 D8, D9, D10, D11, D12, D13, D14, D15,
515 D16, D17, D18, D19, D20, D21, D22, D23,
516 D24, D25, D26, D27, D28, D29, D30, D31]> {
517 let MethodProtos = [{
518 iterator allocation_order_begin(const MachineFunction &MF) const;
519 iterator allocation_order_end(const MachineFunction &MF) const;
521 let MethodBodies = [{
523 static const unsigned ARM_DPR_VFP2[] = {
524 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
525 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
526 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
527 ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
529 static const unsigned ARM_DPR_VFP3[] = {
530 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
531 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
532 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
533 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
534 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
535 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
536 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
537 ARM::D28, ARM::D29, ARM::D30, ARM::D31 };
539 DPRClass::allocation_order_begin(const MachineFunction &MF) const {
540 const TargetMachine &TM = MF.getTarget();
541 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
542 if (Subtarget.hasVFP3())
548 DPRClass::allocation_order_end(const MachineFunction &MF) const {
549 const TargetMachine &TM = MF.getTarget();
550 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
551 if (Subtarget.hasVFP3())
552 return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned));
554 return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned));
559 // Subset of DPR that are accessible with VFP2 (and so that also have
560 // 32-bit SPR subregs).
561 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
562 [D0, D1, D2, D3, D4, D5, D6, D7,
563 D8, D9, D10, D11, D12, D13, D14, D15]> {
564 let SubRegClasses = [(SPR ssub_0, ssub_1)];
567 // Subset of DPR which can be used as a source of NEON scalars for 16-bit
569 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
570 [D0, D1, D2, D3, D4, D5, D6, D7]> {
571 let SubRegClasses = [(SPR_8 ssub_0, ssub_1)];
574 // Generic 128-bit vector register class.
575 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
576 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
577 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> {
578 let SubRegClasses = [(DPR dsub_0, dsub_1)];
581 // Subset of QPR that have 32-bit SPR subregs.
582 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
584 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]> {
585 let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
586 (DPR_VFP2 dsub_0, dsub_1)];
589 // Subset of QPR that have DPR_8 and SPR_8 subregs.
590 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
593 let SubRegClasses = [(SPR_8 ssub_0, ssub_1, ssub_2, ssub_3),
594 (DPR_8 dsub_0, dsub_1)];
597 // Pseudo 256-bit vector register class to model pairs of Q registers
598 // (4 consecutive D registers).
599 def QQPR : RegisterClass<"ARM", [v4i64],
601 [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7]> {
602 let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3),
603 (QPR qsub_0, qsub_1)];
606 // Subset of QQPR that have 32-bit SPR subregs.
607 def QQPR_VFP2 : RegisterClass<"ARM", [v4i64],
609 [QQ0, QQ1, QQ2, QQ3]> {
610 let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
611 (DPR_VFP2 dsub_0, dsub_1, dsub_2, dsub_3),
612 (QPR_VFP2 qsub_0, qsub_1)];
616 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
617 // (8 consecutive D registers).
618 def QQQQPR : RegisterClass<"ARM", [v8i64],
620 [QQQQ0, QQQQ1, QQQQ2, QQQQ3]> {
621 let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3,
622 dsub_4, dsub_5, dsub_6, dsub_7),
623 (QPR qsub_0, qsub_1, qsub_2, qsub_3)];
626 // Condition code registers.
627 def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;