1 //===- ARMRegisterInfo.td - ARM Register defs ----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
12 // Declarations that describe the ARM register file
13 //===----------------------------------------------------------------------===//
15 // Registers are identified with 4-bit ID numbers.
16 class ARMReg<bits<4> num, string n> : Register<n> {
18 let Namespace = "ARM";
22 def R0 : ARMReg< 0, "R0">, DwarfRegNum<0>;
23 def R1 : ARMReg< 1, "R1">, DwarfRegNum<1>;
24 def R2 : ARMReg< 2, "R2">, DwarfRegNum<2>;
25 def R3 : ARMReg< 3, "R3">, DwarfRegNum<3>;
26 def R4 : ARMReg< 4, "R4">, DwarfRegNum<4>;
27 def R5 : ARMReg< 5, "R5">, DwarfRegNum<5>;
28 def R6 : ARMReg< 6, "R6">, DwarfRegNum<6>;
29 def R7 : ARMReg< 7, "R7">, DwarfRegNum<7>;
30 def R8 : ARMReg< 8, "R8">, DwarfRegNum<8>;
31 def R9 : ARMReg< 9, "R9">, DwarfRegNum<9>;
32 def R10 : ARMReg<10, "R10">, DwarfRegNum<10>;
33 def R11 : ARMReg<11, "R11">, DwarfRegNum<11>;
34 def R12 : ARMReg<12, "R12">, DwarfRegNum<12>;
35 def R13 : ARMReg<13, "R13">, DwarfRegNum<13>;
36 def R14 : ARMReg<14, "R14">, DwarfRegNum<14>;
37 def R15 : ARMReg<15, "R15">, DwarfRegNum<15>;
41 // FIXME: the register order should be defined in terms of the preferred
42 // allocation order...
44 def IntRegs : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
45 R7, R8, R9, R10, R11, R12,
48 iterator allocation_order_end(const MachineFunction &MF) const;
51 IntRegsClass::iterator
52 IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
53 // r15 == Program Counter
54 // r14 == Link Register
55 // r13 == Stack Pointer
56 // r12 == ip (scratch)
57 // r11 == Frame Pointer