1 //===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Functional units across ARM processors
13 def FU_Pipe0 : FuncUnit; // pipeline 0 issue
14 def FU_Pipe1 : FuncUnit; // pipeline 1 issue
15 def FU_LdSt0 : FuncUnit; // pipeline 0 load/store
16 def FU_LdSt1 : FuncUnit; // pipeline 1 load/store
18 //===----------------------------------------------------------------------===//
19 // Instruction Itinerary classes used for ARM
21 def IIC_iALU : InstrItinClass;
22 def IIC_iLoad : InstrItinClass;
23 def IIC_iStore : InstrItinClass;
24 def IIC_fpALU : InstrItinClass;
25 def IIC_fpLoad : InstrItinClass;
26 def IIC_fpStore : InstrItinClass;
27 def IIC_Br : InstrItinClass;
29 //===----------------------------------------------------------------------===//
30 // Processor instruction itineraries.
32 def GenericItineraries : ProcessorItineraries<[
33 InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>,
34 InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
35 InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
36 InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>,
37 InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>,
38 InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
39 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>
43 include "ARMScheduleV6.td"
44 include "ARMScheduleV7.td"