lib/Target/ARM/ARMSchedule.td

   1 //===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 //===----------------------------------------------------------------------===//
  11 // Functional units across ARM processors
  12 //
  13 def FU_Issue   : FuncUnit; // issue
  14 def FU_Pipe0   : FuncUnit; // pipeline 0
  15 def FU_Pipe1   : FuncUnit; // pipeline 1
  16 def FU_LdSt0   : FuncUnit; // pipeline 0 load/store
  17 def FU_LdSt1   : FuncUnit; // pipeline 1 load/store
  18 def FU_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  19 def FU_NLSPipe : FuncUnit; // NEON LS pipe
  20
  21 //===----------------------------------------------------------------------===//
  22 // Instruction Itinerary classes used for ARM
  23 //
  24 def IIC_iALUx      : InstrItinClass;
  25 def IIC_iALUi      : InstrItinClass;
  26 def IIC_iALUr      : InstrItinClass;
  27 def IIC_iALUsi     : InstrItinClass;
  28 def IIC_iALUsr     : InstrItinClass;
  29 def IIC_iUNAr      : InstrItinClass;
  30 def IIC_iUNAsi     : InstrItinClass;
  31 def IIC_iUNAsr     : InstrItinClass;
  32 def IIC_iCMPi      : InstrItinClass;
  33 def IIC_iCMPr      : InstrItinClass;
  34 def IIC_iCMPsi     : InstrItinClass;
  35 def IIC_iCMPsr     : InstrItinClass;
  36 def IIC_iMOVi      : InstrItinClass;
  37 def IIC_iMOVr      : InstrItinClass;
  38 def IIC_iMOVsi     : InstrItinClass;
  39 def IIC_iMOVsr     : InstrItinClass;
  40 def IIC_iCMOVi     : InstrItinClass;
  41 def IIC_iCMOVr     : InstrItinClass;
  42 def IIC_iCMOVsi    : InstrItinClass;
  43 def IIC_iCMOVsr    : InstrItinClass;
  44 def IIC_iMUL16     : InstrItinClass;
  45 def IIC_iMAC16     : InstrItinClass;
  46 def IIC_iMUL32     : InstrItinClass;
  47 def IIC_iMAC32     : InstrItinClass;
  48 def IIC_iMUL64     : InstrItinClass;
  49 def IIC_iMAC64     : InstrItinClass;
  50 def IIC_iLoadi     : InstrItinClass;
  51 def IIC_iLoadr     : InstrItinClass;
  52 def IIC_iLoadsi    : InstrItinClass;
  53 def IIC_iLoadiu    : InstrItinClass;
  54 def IIC_iLoadru    : InstrItinClass;
  55 def IIC_iLoadsiu   : InstrItinClass;
  56 def IIC_iLoadm     : InstrItinClass;
  57 def IIC_iStorei    : InstrItinClass;
  58 def IIC_iStorer    : InstrItinClass;
  59 def IIC_iStoresi   : InstrItinClass;
  60 def IIC_iStoreiu   : InstrItinClass;
  61 def IIC_iStoreru   : InstrItinClass;
  62 def IIC_iStoresiu  : InstrItinClass;
  63 def IIC_iStorem    : InstrItinClass;
  64 def IIC_fpSTAT     : InstrItinClass;
  65 def IIC_fpMOVIS    : InstrItinClass;
  66 def IIC_fpMOVID    : InstrItinClass;
  67 def IIC_fpMOVSI    : InstrItinClass;
  68 def IIC_fpMOVDI    : InstrItinClass;
  69 def IIC_fpUNA32    : InstrItinClass;
  70 def IIC_fpUNA64    : InstrItinClass;
  71 def IIC_fpCMP32    : InstrItinClass;
  72 def IIC_fpCMP64    : InstrItinClass;
  73 def IIC_fpCVTSD    : InstrItinClass;
  74 def IIC_fpCVTDS    : InstrItinClass;
  75 def IIC_fpCVTIS    : InstrItinClass;
  76 def IIC_fpCVTID    : InstrItinClass;
  77 def IIC_fpCVTSI    : InstrItinClass;
  78 def IIC_fpCVTDI    : InstrItinClass;
  79 def IIC_fpALU32    : InstrItinClass;
  80 def IIC_fpALU64    : InstrItinClass;
  81 def IIC_fpMUL32    : InstrItinClass;
  82 def IIC_fpMUL64    : InstrItinClass;
  83 def IIC_fpMAC32    : InstrItinClass;
  84 def IIC_fpMAC64    : InstrItinClass;
  85 def IIC_fpDIV32    : InstrItinClass;
  86 def IIC_fpDIV64    : InstrItinClass;
  87 def IIC_fpSQRT32   : InstrItinClass;
  88 def IIC_fpSQRT64   : InstrItinClass;
  89 def IIC_fpLoad32   : InstrItinClass;
  90 def IIC_fpLoad64   : InstrItinClass;
  91 def IIC_fpLoadm    : InstrItinClass;
  92 def IIC_fpStore32  : InstrItinClass;
  93 def IIC_fpStore64  : InstrItinClass;
  94 def IIC_fpStorem   : InstrItinClass;
  95 def IIC_Br         : InstrItinClass;
  96
  97 //===----------------------------------------------------------------------===//
  98 // Processor instruction itineraries.
  99
 100 def GenericItineraries : ProcessorItineraries<[
 101   InstrItinData<IIC_iALUx   , [InstrStage<1, [FU_Pipe0]>]>,
 102   InstrItinData<IIC_iALUi   , [InstrStage<1, [FU_Pipe0]>]>,
 103   InstrItinData<IIC_iALUr   , [InstrStage<1, [FU_Pipe0]>]>,
 104   InstrItinData<IIC_iALUsi  , [InstrStage<1, [FU_Pipe0]>]>,
 105   InstrItinData<IIC_iALUsr  , [InstrStage<1, [FU_Pipe0]>]>,
 106   InstrItinData<IIC_iUNAr   , [InstrStage<1, [FU_Pipe0]>]>,
 107   InstrItinData<IIC_iUNAsi  , [InstrStage<1, [FU_Pipe0]>]>,
 108   InstrItinData<IIC_iUNAsr  , [InstrStage<1, [FU_Pipe0]>]>,
 109   InstrItinData<IIC_iCMPi   , [InstrStage<1, [FU_Pipe0]>]>,
 110   InstrItinData<IIC_iCMPr   , [InstrStage<1, [FU_Pipe0]>]>,
 111   InstrItinData<IIC_iCMPsi  , [InstrStage<1, [FU_Pipe0]>]>,
 112   InstrItinData<IIC_iCMPsr  , [InstrStage<1, [FU_Pipe0]>]>,
 113   InstrItinData<IIC_iMOVi   , [InstrStage<1, [FU_Pipe0]>]>,
 114   InstrItinData<IIC_iMOVr   , [InstrStage<1, [FU_Pipe0]>]>,
 115   InstrItinData<IIC_iMOVsi  , [InstrStage<1, [FU_Pipe0]>]>,
 116   InstrItinData<IIC_iMOVsr  , [InstrStage<1, [FU_Pipe0]>]>,
 117   InstrItinData<IIC_iCMOVi  , [InstrStage<1, [FU_Pipe0]>]>,
 118   InstrItinData<IIC_iCMOVr  , [InstrStage<1, [FU_Pipe0]>]>,
 119   InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
 120   InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
 121   InstrItinData<IIC_iMUL16  , [InstrStage<1, [FU_Pipe0]>]>,
 122   InstrItinData<IIC_iMAC16  , [InstrStage<1, [FU_Pipe0]>]>,
 123   InstrItinData<IIC_iMUL32  , [InstrStage<1, [FU_Pipe0]>]>,
 124   InstrItinData<IIC_iMAC32  , [InstrStage<1, [FU_Pipe0]>]>,
 125   InstrItinData<IIC_iMUL64  , [InstrStage<1, [FU_Pipe0]>]>,
 126   InstrItinData<IIC_iMAC64  , [InstrStage<1, [FU_Pipe0]>]>,
 127   InstrItinData<IIC_iLoadi  , [InstrStage<1, [FU_Pipe0]>,
 128                                InstrStage<1, [FU_LdSt0]>]>,
 129   InstrItinData<IIC_iLoadr  , [InstrStage<1, [FU_Pipe0]>,
 130                                InstrStage<1, [FU_LdSt0]>]>,
 131   InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
 132                                InstrStage<1, [FU_LdSt0]>]>,
 133   InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
 134                                InstrStage<1, [FU_LdSt0]>]>,
 135   InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
 136                                InstrStage<1, [FU_LdSt0]>]>,
 137   InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
 138                                InstrStage<1, [FU_LdSt0]>]>,
 139   InstrItinData<IIC_iLoadm  , [InstrStage<2, [FU_Pipe0]>,
 140                                InstrStage<2, [FU_LdSt0]>]>,
 141   InstrItinData<IIC_iStorei  , [InstrStage<1, [FU_Pipe0]>]>,
 142   InstrItinData<IIC_iStorer  , [InstrStage<1, [FU_Pipe0]>]>,
 143   InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
 144   InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
 145   InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
 146   InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
 147   InstrItinData<IIC_iStorem  , [InstrStage<2, [FU_Pipe0]>]>,
 148   InstrItinData<IIC_Br       , [InstrStage<1, [FU_Pipe0]>]>,
 149   InstrItinData<IIC_fpSTAT   , [InstrStage<1, [FU_Pipe0]>]>,
 150   InstrItinData<IIC_fpMOVSI  , [InstrStage<1, [FU_Pipe0]>]>,
 151   InstrItinData<IIC_fpMOVDI  , [InstrStage<1, [FU_Pipe0]>]>,
 152   InstrItinData<IIC_fpMOVIS  , [InstrStage<1, [FU_Pipe0]>]>,
 153   InstrItinData<IIC_fpMOVID  , [InstrStage<1, [FU_Pipe0]>]>,
 154   InstrItinData<IIC_fpUNA32  , [InstrStage<1, [FU_Pipe0]>]>,
 155   InstrItinData<IIC_fpUNA64  , [InstrStage<1, [FU_Pipe0]>]>,
 156   InstrItinData<IIC_fpCMP32  , [InstrStage<1, [FU_Pipe0]>]>,
 157   InstrItinData<IIC_fpCMP64  , [InstrStage<1, [FU_Pipe0]>]>,
 158   InstrItinData<IIC_fpCVTSD  , [InstrStage<1, [FU_Pipe0]>]>,
 159   InstrItinData<IIC_fpCVTDS  , [InstrStage<1, [FU_Pipe0]>]>,
 160   InstrItinData<IIC_fpCVTIS  , [InstrStage<1, [FU_Pipe0]>]>,
 161   InstrItinData<IIC_fpCVTID  , [InstrStage<1, [FU_Pipe0]>]>,
 162   InstrItinData<IIC_fpCVTSI  , [InstrStage<1, [FU_Pipe0]>]>,
 163   InstrItinData<IIC_fpCVTDI  , [InstrStage<1, [FU_Pipe0]>]>,
 164   InstrItinData<IIC_fpALU32  , [InstrStage<1, [FU_Pipe0]>]>,
 165   InstrItinData<IIC_fpALU64  , [InstrStage<1, [FU_Pipe0]>]>,
 166   InstrItinData<IIC_fpMUL32  , [InstrStage<1, [FU_Pipe0]>]>,
 167   InstrItinData<IIC_fpMUL64  , [InstrStage<1, [FU_Pipe0]>]>,
 168   InstrItinData<IIC_fpMAC32  , [InstrStage<1, [FU_Pipe0]>]>,
 169   InstrItinData<IIC_fpMAC64  , [InstrStage<1, [FU_Pipe0]>]>,
 170   InstrItinData<IIC_fpDIV32  , [InstrStage<1, [FU_Pipe0]>]>,
 171   InstrItinData<IIC_fpDIV64  , [InstrStage<1, [FU_Pipe0]>]>,
 172   InstrItinData<IIC_fpSQRT32 , [InstrStage<1, [FU_Pipe0]>]>,
 173   InstrItinData<IIC_fpSQRT64 , [InstrStage<1, [FU_Pipe0]>]>,
 174   InstrItinData<IIC_fpLoad32 , [InstrStage<1, [FU_Pipe0]>,
 175                                 InstrStage<1, [FU_LdSt0]>]>,
 176   InstrItinData<IIC_fpLoad64 , [InstrStage<1, [FU_Pipe0]>,
 177                                 InstrStage<1, [FU_LdSt0]>]>,
 178   InstrItinData<IIC_fpLoadm  , [InstrStage<1, [FU_Pipe0]>,
 179                                 InstrStage<1, [FU_LdSt0]>]>,
 180   InstrItinData<IIC_fpStore32, [InstrStage<1, [FU_Pipe0]>]>,
 181   InstrItinData<IIC_fpStore64, [InstrStage<1, [FU_Pipe0]>]>,
 182   InstrItinData<IIC_fpStorem , [InstrStage<1, [FU_Pipe0]>]>
 183 ]>;
 184
 185
 186 include "ARMScheduleV6.td"
 187 include "ARMScheduleV7.td"