1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
12 //===----------------------------------------------------------------------===//
15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
17 def A8_Pipe0 : FuncUnit; // pipeline 0
18 def A8_Pipe1 : FuncUnit; // pipeline 1
19 def A8_LSPipe : FuncUnit; // Load / store pipeline
20 def A8_NPipe : FuncUnit; // NEON ALU/MUL pipe
21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
25 def CortexA8Itineraries : ProcessorItineraries<
26 [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
28 // Two fully-pipelined integer ALU pipelines
31 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
33 // Binary Instructions that produce a result
34 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
35 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
36 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
37 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
40 // Bitwise Instructions that produce a result
41 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
42 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
43 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
44 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
46 // Unary Instructions that produce a result
47 InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
48 InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
50 // Zero and sign extension instructions
51 InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
52 InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
53 InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
55 // Compare instructions
56 InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
57 InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
58 InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
59 InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
62 InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
63 InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
64 InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
65 InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
67 // Move instructions, unconditional
68 InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
69 InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
70 InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
71 InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
72 InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
73 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
75 // Move instructions, conditional
76 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
77 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
78 InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
79 InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
80 InstrItinData<IIC_iCMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
81 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3, 1]>,
84 InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
85 InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
86 InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
87 InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
89 // Integer multiply pipeline
90 // Result written in E5, but that is relative to the last cycle of multicycle,
91 // so we use 6 for those cases
93 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
94 InstrItinData<IIC_iMAC16 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
95 InstrItinData<IIC_iMUL32 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
96 InstrItinData<IIC_iMAC32 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
97 InstrItinData<IIC_iMUL64 , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
98 InstrItinData<IIC_iMAC64 , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
100 // Integer load pipeline
103 InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
104 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
105 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
106 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
107 InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
108 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
111 InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
112 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
113 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
114 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
115 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
116 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
118 // Scaled register offset, issues over 2 cycles
119 // FIXME: lsl by 2 takes 1 cycle.
120 InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
121 InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
122 InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
123 InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
125 // Immediate offset with update
126 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
127 InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
128 InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
129 InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
131 // Register offset with update
132 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
133 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
134 InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
135 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
136 InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
137 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
139 // Scaled register offset with update, issues over 2 cycles
140 InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
141 InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
142 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
143 InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
145 // Load multiple, def is the 5th operand. Pipeline 0 only.
146 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
147 InstrItinData<IIC_iLoad_m , [InstrStage<2, [A8_Pipe0], 0>,
148 InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
150 // Load multiple + update, defs are the 1st and 5th operands.
151 InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>,
152 InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
154 // Load multiple plus branch
155 InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>,
156 InstrStage<3, [A8_LSPipe]>,
157 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
160 // Pop, def is the 3rd operand.
161 InstrItinData<IIC_iPop , [InstrStage<3, [A8_Pipe0], 0>,
162 InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
164 // Push, def is the 3th operand.
165 InstrItinData<IIC_iPop_Br, [InstrStage<3, [A8_Pipe0], 0>,
166 InstrStage<3, [A8_LSPipe]>,
167 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
171 // iLoadi + iALUr for t2LDRpci_pic.
172 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
173 InstrStage<1, [A8_LSPipe]>,
174 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
177 // Integer store pipeline
180 InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
181 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
182 InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
183 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
184 InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
185 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
188 InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
189 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
190 InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
191 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
192 InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
193 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
195 // Scaled register offset, issues over 2 cycles
196 InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
197 InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
198 InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
199 InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
201 // Immediate offset with update
202 InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
203 InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
204 InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
205 InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
207 // Register offset with update
208 InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
209 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
210 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
211 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
212 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
213 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
215 // Scaled register offset with update, issues over 2 cycles
216 InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
217 InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
218 InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
219 InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
221 // Store multiple. Pipeline 0 only.
222 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
223 InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>,
224 InstrStage<2, [A8_LSPipe]>]>,
226 // Store multiple + update
227 InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>,
228 InstrStage<2, [A8_LSPipe]>], [2]>,
232 InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
236 // no delay slots, so the latency of a branch is unimportant
237 InstrItinData<IIC_Br , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
240 // Issue through integer pipeline, and execute in NEON unit. We assume
241 // RunFast mode so that NFP pipeline is used for single-precision when
244 // FP Special Register to Integer Register File Move
245 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
246 InstrStage<1, [A8_NLSPipe]>], [20]>,
248 // Single-precision FP Unary
249 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
250 InstrStage<1, [A8_NPipe]>], [7, 1]>,
252 // Double-precision FP Unary
253 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
254 InstrStage<4, [A8_NPipe], 0>,
255 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
257 // Single-precision FP Compare
258 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
259 InstrStage<1, [A8_NPipe]>], [1, 1]>,
261 // Double-precision FP Compare
262 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
263 InstrStage<4, [A8_NPipe], 0>,
264 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
266 // Single to Double FP Convert
267 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
268 InstrStage<7, [A8_NPipe], 0>,
269 InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
271 // Double to Single FP Convert
272 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
273 InstrStage<5, [A8_NPipe], 0>,
274 InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
276 // Single-Precision FP to Integer Convert
277 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
278 InstrStage<1, [A8_NPipe]>], [7, 1]>,
280 // Double-Precision FP to Integer Convert
281 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
282 InstrStage<8, [A8_NPipe], 0>,
283 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
285 // Integer to Single-Precision FP Convert
286 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
287 InstrStage<1, [A8_NPipe]>], [7, 1]>,
289 // Integer to Double-Precision FP Convert
290 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
291 InstrStage<8, [A8_NPipe], 0>,
292 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
294 // Single-precision FP ALU
295 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
296 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
298 // Double-precision FP ALU
299 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
300 InstrStage<9, [A8_NPipe], 0>,
301 InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
303 // Single-precision FP Multiply
304 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
305 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
307 // Double-precision FP Multiply
308 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
309 InstrStage<11, [A8_NPipe], 0>,
310 InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
312 // Single-precision FP MAC
313 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
314 InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
316 // Double-precision FP MAC
317 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
318 InstrStage<19, [A8_NPipe], 0>,
319 InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
321 // Single-precision FP DIV
322 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
323 InstrStage<20, [A8_NPipe], 0>,
324 InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
326 // Double-precision FP DIV
327 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
328 InstrStage<29, [A8_NPipe], 0>,
329 InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
331 // Single-precision FP SQRT
332 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
333 InstrStage<19, [A8_NPipe], 0>,
334 InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
336 // Double-precision FP SQRT
337 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
338 InstrStage<29, [A8_NPipe], 0>,
339 InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
342 // Integer to Single-precision Move
343 InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
344 InstrStage<1, [A8_NPipe]>],
347 // Integer to Double-precision Move
348 InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
349 InstrStage<1, [A8_NPipe]>],
352 // Single-precision to Integer Move
353 InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
354 InstrStage<1, [A8_NPipe]>],
357 // Double-precision to Integer Move
358 InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
359 InstrStage<1, [A8_NPipe]>],
363 // Single-precision FP Load
364 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
365 InstrStage<1, [A8_NLSPipe], 0>,
366 InstrStage<1, [A8_LSPipe]>],
369 // Double-precision FP Load
370 InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
371 InstrStage<1, [A8_NLSPipe], 0>,
372 InstrStage<1, [A8_LSPipe]>],
376 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
377 InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
378 InstrStage<1, [A8_NLSPipe], 0>,
379 InstrStage<1, [A8_LSPipe]>,
380 InstrStage<1, [A8_NLSPipe], 0>,
381 InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
383 // FP Load Multiple + update
384 InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
385 InstrStage<1, [A8_NLSPipe], 0>,
386 InstrStage<1, [A8_LSPipe]>,
387 InstrStage<1, [A8_NLSPipe], 0>,
388 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
390 // Single-precision FP Store
391 InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
392 InstrStage<1, [A8_NLSPipe], 0>,
393 InstrStage<1, [A8_LSPipe]>],
396 // Double-precision FP Store
397 InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
398 InstrStage<1, [A8_NLSPipe], 0>,
399 InstrStage<1, [A8_LSPipe]>],
403 InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
404 InstrStage<1, [A8_NLSPipe], 0>,
405 InstrStage<1, [A8_LSPipe]>,
406 InstrStage<1, [A8_NLSPipe], 0>,
407 InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
409 // FP Store Multiple + update
410 InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
411 InstrStage<1, [A8_NLSPipe], 0>,
412 InstrStage<1, [A8_LSPipe]>,
413 InstrStage<1, [A8_NLSPipe], 0>,
414 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
417 // Issue through integer pipeline, and execute in NEON unit.
420 InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
421 InstrStage<2, [A8_NLSPipe], 0>,
422 InstrStage<2, [A8_LSPipe]>],
425 InstrItinData<IIC_VLD1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
426 InstrStage<2, [A8_NLSPipe], 0>,
427 InstrStage<2, [A8_LSPipe]>],
431 InstrItinData<IIC_VLD1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
432 InstrStage<3, [A8_NLSPipe], 0>,
433 InstrStage<3, [A8_LSPipe]>],
437 InstrItinData<IIC_VLD1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
438 InstrStage<3, [A8_NLSPipe], 0>,
439 InstrStage<3, [A8_LSPipe]>],
443 InstrItinData<IIC_VLD1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
444 InstrStage<2, [A8_NLSPipe], 0>,
445 InstrStage<2, [A8_LSPipe]>],
449 InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
450 InstrStage<2, [A8_NLSPipe], 0>,
451 InstrStage<2, [A8_LSPipe]>],
455 InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
456 InstrStage<3, [A8_NLSPipe], 0>,
457 InstrStage<3, [A8_LSPipe]>],
461 InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
462 InstrStage<3, [A8_NLSPipe], 0>,
463 InstrStage<3, [A8_LSPipe]>],
467 InstrItinData<IIC_VLD1ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
468 InstrStage<3, [A8_NLSPipe], 0>,
469 InstrStage<3, [A8_LSPipe]>],
473 InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
474 InstrStage<3, [A8_NLSPipe], 0>,
475 InstrStage<3, [A8_LSPipe]>],
479 InstrItinData<IIC_VLD1dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
480 InstrStage<2, [A8_NLSPipe], 0>,
481 InstrStage<2, [A8_LSPipe]>],
485 InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
486 InstrStage<2, [A8_NLSPipe], 0>,
487 InstrStage<2, [A8_LSPipe]>],
491 InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
492 InstrStage<2, [A8_NLSPipe], 0>,
493 InstrStage<2, [A8_LSPipe]>],
497 InstrItinData<IIC_VLD2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
498 InstrStage<3, [A8_NLSPipe], 0>,
499 InstrStage<3, [A8_LSPipe]>],
503 InstrItinData<IIC_VLD2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
504 InstrStage<3, [A8_NLSPipe], 0>,
505 InstrStage<3, [A8_LSPipe]>],
509 InstrItinData<IIC_VLD2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
510 InstrStage<2, [A8_NLSPipe], 0>,
511 InstrStage<2, [A8_LSPipe]>],
515 InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
516 InstrStage<3, [A8_NLSPipe], 0>,
517 InstrStage<3, [A8_LSPipe]>],
521 InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
522 InstrStage<3, [A8_NLSPipe], 0>,
523 InstrStage<3, [A8_LSPipe]>],
524 [3, 3, 2, 1, 1, 1, 1, 1]>,
527 InstrItinData<IIC_VLD2dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
528 InstrStage<2, [A8_NLSPipe], 0>,
529 InstrStage<2, [A8_LSPipe]>],
533 InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
534 InstrStage<2, [A8_NLSPipe], 0>,
535 InstrStage<2, [A8_LSPipe]>],
539 InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
540 InstrStage<4, [A8_NLSPipe], 0>,
541 InstrStage<4, [A8_LSPipe]>],
545 InstrItinData<IIC_VLD3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
546 InstrStage<5, [A8_NLSPipe], 0>,
547 InstrStage<5, [A8_LSPipe]>],
548 [4, 4, 5, 1, 1, 1, 1, 2]>,
551 InstrItinData<IIC_VLD3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
552 InstrStage<4, [A8_NLSPipe], 0>,
553 InstrStage<4, [A8_LSPipe]>],
557 InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
558 InstrStage<5, [A8_NLSPipe], 0>,
559 InstrStage<5, [A8_LSPipe]>],
560 [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
563 InstrItinData<IIC_VLD3dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
564 InstrStage<3, [A8_NLSPipe], 0>,
565 InstrStage<3, [A8_LSPipe]>],
569 InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
570 InstrStage<3, [A8_NLSPipe], 0>,
571 InstrStage<3, [A8_LSPipe]>],
575 InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
576 InstrStage<4, [A8_NLSPipe], 0>,
577 InstrStage<4, [A8_LSPipe]>],
581 InstrItinData<IIC_VLD4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
582 InstrStage<5, [A8_NLSPipe], 0>,
583 InstrStage<5, [A8_LSPipe]>],
584 [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
587 InstrItinData<IIC_VLD4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
588 InstrStage<4, [A8_NLSPipe], 0>,
589 InstrStage<4, [A8_LSPipe]>],
593 InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
594 InstrStage<5, [A8_NLSPipe], 0>,
595 InstrStage<5, [A8_LSPipe]>],
596 [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
599 InstrItinData<IIC_VLD4dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
600 InstrStage<3, [A8_NLSPipe], 0>,
601 InstrStage<3, [A8_LSPipe]>],
605 InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
606 InstrStage<3, [A8_NLSPipe], 0>,
607 InstrStage<3, [A8_LSPipe]>],
608 [2, 2, 3, 3, 2, 1, 1]>,
611 InstrItinData<IIC_VST1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
612 InstrStage<2, [A8_NLSPipe], 0>,
613 InstrStage<2, [A8_LSPipe]>],
617 InstrItinData<IIC_VST1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
618 InstrStage<2, [A8_NLSPipe], 0>,
619 InstrStage<2, [A8_LSPipe]>],
623 InstrItinData<IIC_VST1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
624 InstrStage<3, [A8_NLSPipe], 0>,
625 InstrStage<3, [A8_LSPipe]>],
629 InstrItinData<IIC_VST1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
630 InstrStage<3, [A8_NLSPipe], 0>,
631 InstrStage<3, [A8_LSPipe]>],
635 InstrItinData<IIC_VST1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
636 InstrStage<2, [A8_NLSPipe], 0>,
637 InstrStage<2, [A8_LSPipe]>],
641 InstrItinData<IIC_VST1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
642 InstrStage<2, [A8_NLSPipe], 0>,
643 InstrStage<2, [A8_LSPipe]>],
647 InstrItinData<IIC_VST1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
648 InstrStage<3, [A8_NLSPipe], 0>,
649 InstrStage<3, [A8_LSPipe]>],
650 [2, 1, 1, 1, 1, 1, 2]>,
653 InstrItinData<IIC_VST1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
654 InstrStage<3, [A8_NLSPipe], 0>,
655 InstrStage<3, [A8_LSPipe]>],
656 [2, 1, 1, 1, 1, 1, 2, 2]>,
659 InstrItinData<IIC_VST1ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
660 InstrStage<2, [A8_NLSPipe], 0>,
661 InstrStage<2, [A8_LSPipe]>],
665 InstrItinData<IIC_VST1lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
666 InstrStage<2, [A8_NLSPipe], 0>,
667 InstrStage<2, [A8_LSPipe]>],
671 InstrItinData<IIC_VST2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
672 InstrStage<2, [A8_NLSPipe], 0>,
673 InstrStage<2, [A8_LSPipe]>],
677 InstrItinData<IIC_VST2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
678 InstrStage<4, [A8_NLSPipe], 0>,
679 InstrStage<4, [A8_LSPipe]>],
683 InstrItinData<IIC_VST2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
684 InstrStage<2, [A8_NLSPipe], 0>,
685 InstrStage<2, [A8_LSPipe]>],
689 InstrItinData<IIC_VST2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
690 InstrStage<4, [A8_NLSPipe], 0>,
691 InstrStage<4, [A8_LSPipe]>],
692 [2, 1, 1, 1, 1, 1, 2, 2]>,
695 InstrItinData<IIC_VST2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
696 InstrStage<2, [A8_NLSPipe], 0>,
697 InstrStage<2, [A8_LSPipe]>],
701 InstrItinData<IIC_VST2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
702 InstrStage<2, [A8_NLSPipe], 0>,
703 InstrStage<2, [A8_LSPipe]>],
707 InstrItinData<IIC_VST3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
708 InstrStage<3, [A8_NLSPipe], 0>,
709 InstrStage<3, [A8_LSPipe]>],
713 InstrItinData<IIC_VST3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
714 InstrStage<3, [A8_NLSPipe], 0>,
715 InstrStage<3, [A8_LSPipe]>],
716 [2, 1, 1, 1, 1, 1, 2]>,
719 InstrItinData<IIC_VST3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
720 InstrStage<3, [A8_NLSPipe], 0>,
721 InstrStage<3, [A8_LSPipe]>],
725 InstrItinData<IIC_VST3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
726 InstrStage<3, [A8_NLSPipe], 0>,
727 InstrStage<3, [A8_LSPipe]>],
728 [2, 1, 1, 1, 1, 1, 2]>,
731 InstrItinData<IIC_VST4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
732 InstrStage<4, [A8_NLSPipe], 0>,
733 InstrStage<4, [A8_LSPipe]>],
737 InstrItinData<IIC_VST4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
738 InstrStage<4, [A8_NLSPipe], 0>,
739 InstrStage<4, [A8_LSPipe]>],
740 [2, 1, 1, 1, 1, 1, 2, 2]>,
743 InstrItinData<IIC_VST4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
744 InstrStage<4, [A8_NLSPipe], 0>,
745 InstrStage<4, [A8_LSPipe]>],
749 InstrItinData<IIC_VST4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
750 InstrStage<4, [A8_NLSPipe], 0>,
751 InstrStage<4, [A8_LSPipe]>],
752 [2, 1, 1, 1, 1, 1, 2, 2]>,
754 // Double-register FP Unary
755 InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
756 InstrStage<1, [A8_NPipe]>], [5, 2]>,
758 // Quad-register FP Unary
759 // Result written in N5, but that is relative to the last cycle of multicycle,
760 // so we use 6 for those cases
761 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
762 InstrStage<2, [A8_NPipe]>], [6, 2]>,
764 // Double-register FP Binary
765 InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
766 InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
769 InstrItinData<IIC_VPBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
770 InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
772 // Double-register FP VMUL
773 InstrItinData<IIC_VFMULD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
774 InstrStage<1, [A8_NPipe]>], [5, 2, 1]>,
777 // Quad-register FP Binary
778 // Result written in N5, but that is relative to the last cycle of multicycle,
779 // so we use 6 for those cases
780 InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
781 InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
783 // Quad-register FP VMUL
784 InstrItinData<IIC_VFMULQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
785 InstrStage<1, [A8_NPipe]>], [6, 2, 1]>,
788 InstrItinData<IIC_VMOV, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
789 InstrStage<1, [A8_NPipe]>], [1, 1]>,
792 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
793 InstrStage<1, [A8_NPipe]>], [3]>,
795 // Double-register Permute Move
796 InstrItinData<IIC_VMOVD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
797 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
799 // Quad-register Permute Move
800 // Result written in N2, but that is relative to the last cycle of multicycle,
801 // so we use 3 for those cases
802 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
803 InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
805 // Integer to Single-precision Move
806 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
807 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
809 // Integer to Double-precision Move
810 InstrItinData<IIC_VMOVID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
811 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
813 // Single-precision to Integer Move
814 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
815 InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
817 // Double-precision to Integer Move
818 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
819 InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
821 // Integer to Lane Move
822 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
823 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
825 // Vector narrow move
826 InstrItinData<IIC_VMOVN , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
827 InstrStage<1, [A8_NPipe]>], [2, 1]>,
829 // Double-register Permute
830 InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
831 InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
833 // Quad-register Permute
834 // Result written in N2, but that is relative to the last cycle of multicycle,
835 // so we use 3 for those cases
836 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
837 InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
839 // Quad-register Permute (3 cycle issue)
840 // Result written in N2, but that is relative to the last cycle of multicycle,
841 // so we use 4 for those cases
842 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
843 InstrStage<1, [A8_NLSPipe]>,
844 InstrStage<1, [A8_NPipe], 0>,
845 InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
847 // Double-register FP Multiple-Accumulate
848 InstrItinData<IIC_VMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
849 InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
851 // Quad-register FP Multiple-Accumulate
852 // Result written in N9, but that is relative to the last cycle of multicycle,
853 // so we use 10 for those cases
854 InstrItinData<IIC_VMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
855 InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
857 // Double-register Reciprical Step
858 InstrItinData<IIC_VRECSD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
859 InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
861 // Quad-register Reciprical Step
862 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
863 InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
865 // Double-register Integer Count
866 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
867 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
869 // Quad-register Integer Count
870 // Result written in N3, but that is relative to the last cycle of multicycle,
871 // so we use 4 for those cases
872 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
873 InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
875 // Double-register Integer Unary
876 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
877 InstrStage<1, [A8_NPipe]>], [4, 2]>,
879 // Quad-register Integer Unary
880 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
881 InstrStage<1, [A8_NPipe]>], [4, 2]>,
883 // Double-register Integer Q-Unary
884 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
885 InstrStage<1, [A8_NPipe]>], [4, 1]>,
887 // Quad-register Integer CountQ-Unary
888 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
889 InstrStage<1, [A8_NPipe]>], [4, 1]>,
891 // Double-register Integer Binary
892 InstrItinData<IIC_VBINiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
893 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
895 // Quad-register Integer Binary
896 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
897 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
899 // Double-register Integer Binary (4 cycle)
900 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
901 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
903 // Quad-register Integer Binary (4 cycle)
904 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
905 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
908 // Double-register Integer Subtract
909 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
910 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
912 // Quad-register Integer Subtract
913 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
914 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
916 // Double-register Integer Subtract
917 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
918 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
920 // Quad-register Integer Subtract
921 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
922 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
924 // Double-register Integer Shift
925 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
926 InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
928 // Quad-register Integer Shift
929 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
930 InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
932 // Double-register Integer Shift (4 cycle)
933 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
934 InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
936 // Quad-register Integer Shift (4 cycle)
937 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
938 InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
940 // Double-register Integer Pair Add Long
941 InstrItinData<IIC_VPALiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
942 InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
944 // Quad-register Integer Pair Add Long
945 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
946 InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
948 // Double-register Absolute Difference and Accumulate
949 InstrItinData<IIC_VABAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
950 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
952 // Quad-register Absolute Difference and Accumulate
953 InstrItinData<IIC_VABAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
954 InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
957 // Double-register Integer Multiply (.8, .16)
958 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
959 InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
961 // Double-register Integer Multiply (.32)
962 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
963 InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
965 // Quad-register Integer Multiply (.8, .16)
966 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
967 InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
969 // Quad-register Integer Multiply (.32)
970 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
971 InstrStage<1, [A8_NPipe]>,
972 InstrStage<2, [A8_NLSPipe], 0>,
973 InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
975 // Double-register Integer Multiply-Accumulate (.8, .16)
976 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
977 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
979 // Double-register Integer Multiply-Accumulate (.32)
980 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
981 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
983 // Quad-register Integer Multiply-Accumulate (.8, .16)
984 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
985 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
987 // Quad-register Integer Multiply-Accumulate (.32)
988 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
989 InstrStage<1, [A8_NPipe]>,
990 InstrStage<2, [A8_NLSPipe], 0>,
991 InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
993 // Double-register VEXT
994 InstrItinData<IIC_VEXTD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
995 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
997 // Quad-register VEXT
998 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
999 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
1002 InstrItinData<IIC_VTB1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1003 InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
1004 InstrItinData<IIC_VTB2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1005 InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
1006 InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1007 InstrStage<1, [A8_NLSPipe]>,
1008 InstrStage<1, [A8_NPipe], 0>,
1009 InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
1010 InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1011 InstrStage<1, [A8_NLSPipe]>,
1012 InstrStage<1, [A8_NPipe], 0>,
1013 InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
1016 InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1017 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
1018 InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1019 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
1020 InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1021 InstrStage<1, [A8_NLSPipe]>,
1022 InstrStage<1, [A8_NPipe], 0>,
1023 InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
1024 InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1025 InstrStage<1, [A8_NLSPipe]>,
1026 InstrStage<1, [A8_NPipe], 0>,
1027 InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>