lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 // Functional Units.
  17 def A8_Pipe0   : FuncUnit; // pipeline 0
  18 def A8_Pipe1   : FuncUnit; // pipeline 1
  19 def A8_LSPipe  : FuncUnit; // Load / store pipeline
  20 def A8_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
  22 //
  23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
  24 //
  25 def CortexA8Itineraries : MultiIssueItineraries<
  26   2,  // IssueWidth
  27   -1, // MinLatency - OperandCycles are interpreted as MinLatency.
  28   2,  // LoadLatency - overriden by OperandCycles.
  29   10, // HighLatency - currently unused.
  30   [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
  31   [], [
  32   // Two fully-pipelined integer ALU pipelines
  33   //
  34   // No operand cycles
  35   InstrItinData<IIC_iALUx    , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
  36   //
  37   // Binary Instructions that produce a result
  38   InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  39   InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  40   InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  41   InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
  42   InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  43   //
  44   // Bitwise Instructions that produce a result
  45   InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  46   InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  47   InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  48   InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  49   //
  50   // Unary Instructions that produce a result
  51   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  52   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  53   //
  54   // Zero and sign extension instructions
  55   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  56   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  57   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
  58   //
  59   // Compare instructions
  60   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  61   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  62   InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  63   InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  64   //
  65   // Test instructions
  66   InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  67   InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  68   InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  69   InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  70   //
  71   // Move instructions, unconditional
  72   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  73   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  74   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  75   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  76   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  77                              InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  78   InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  79                                   InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  80                                   InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3]>,
  81   InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  82                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  83                                InstrStage<1, [A8_LSPipe]>], [5]>,
  84   //
  85   // Move instructions, conditional
  86   InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  87   InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  88   InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  89   InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  90   InstrItinData<IIC_iCMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  91                               InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3, 1]>,
  92   //
  93   // MVN instructions
  94   InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  95   InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  96   InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  97   InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  98
  99   // Integer multiply pipeline
 100   // Result written in E5, but that is relative to the last cycle of multicycle,
 101   // so we use 6 for those cases
 102   //
 103   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
 104   InstrItinData<IIC_iMAC16   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
 105   InstrItinData<IIC_iMUL32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
 106   InstrItinData<IIC_iMAC32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
 107   InstrItinData<IIC_iMUL64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
 108   InstrItinData<IIC_iMAC64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
 109
 110   // Integer load pipeline
 111   //
 112   // Immediate offset
 113   InstrItinData<IIC_iLoad_i   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 114                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 115   InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 116                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 117   InstrItinData<IIC_iLoad_d_i,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 118                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 119   //
 120   // Register offset
 121   InstrItinData<IIC_iLoad_r   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 122                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 123   InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 124                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 125   InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 126                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 127   //
 128   // Scaled register offset, issues over 2 cycles
 129   // FIXME: lsl by 2 takes 1 cycle.
 130   InstrItinData<IIC_iLoad_si  , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 131                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 132   InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 133                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 134   //
 135   // Immediate offset with update
 136   InstrItinData<IIC_iLoad_iu  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 137                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 138   InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 139                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 140   //
 141   // Register offset with update
 142   InstrItinData<IIC_iLoad_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 143                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 144   InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 145                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 146   InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 147                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 148   //
 149   // Scaled register offset with update, issues over 2 cycles
 150   InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 151                                  InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
 152   InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 153                                   InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
 154   //
 155   // Load multiple, def is the 5th operand. Pipeline 0 only.
 156   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 157   InstrItinData<IIC_iLoad_m  , [InstrStage<2, [A8_Pipe0], 0>,
 158                                 InstrStage<2, [A8_LSPipe]>],
 159                 [1, 1, 1, 1, 3], [], -1>, // dynamic uops
 160   //
 161   // Load multiple + update, defs are the 1st and 5th operands.
 162   InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>,
 163                                 InstrStage<3, [A8_LSPipe]>],
 164                 [2, 1, 1, 1, 3], [], -1>, // dynamic uops
 165   //
 166   // Load multiple plus branch
 167   InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>,
 168                                 InstrStage<3, [A8_LSPipe]>,
 169                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 170                               [1, 2, 1, 1, 3], [], -1>, // dynamic uops
 171   //
 172   // Pop, def is the 3rd operand.
 173   InstrItinData<IIC_iPop  ,    [InstrStage<3, [A8_Pipe0], 0>,
 174                                 InstrStage<3, [A8_LSPipe]>],
 175                 [1, 1, 3], [], -1>, // dynamic uops
 176   //
 177   // Push, def is the 3th operand.
 178   InstrItinData<IIC_iPop_Br,   [InstrStage<3, [A8_Pipe0], 0>,
 179                                 InstrStage<3, [A8_LSPipe]>,
 180                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 181                                [1, 1, 3], [], -1>, // dynamic uops
 182   //
 183   // iLoadi + iALUr for t2LDRpci_pic.
 184   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 185                                 InstrStage<1, [A8_LSPipe]>,
 186                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
 187
 188
 189   // Integer store pipeline
 190   //
 191   // Immediate offset
 192   InstrItinData<IIC_iStore_i  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 193                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 194   InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 195                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 196   InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 197                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 198   //
 199   // Register offset
 200   InstrItinData<IIC_iStore_r  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 201                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 202   InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 203                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 204   InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 205                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 206   //
 207   // Scaled register offset, issues over 2 cycles
 208   InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 209                                  InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 210   InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 211                                   InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 212   //
 213   // Immediate offset with update
 214   InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 215                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 216   InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 217                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 218   //
 219   // Register offset with update
 220   InstrItinData<IIC_iStore_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 221                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 222   InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 223                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 224   InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 225                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 226   //
 227   // Scaled register offset with update, issues over 2 cycles
 228   InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 229                                  InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 230   InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 231                                    InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 232   //
 233   // Store multiple. Pipeline 0 only.
 234   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 235   InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>,
 236                                 InstrStage<2, [A8_LSPipe]>],
 237                 [], [], -1>, // dynamic uops
 238   //
 239   // Store multiple + update
 240   InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>,
 241                                 InstrStage<2, [A8_LSPipe]>],
 242                 [2], [], -1>, // dynamic uops
 243   //
 244   // Preload
 245   InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
 246
 247   // Branch
 248   //
 249   // no delay slots, so the latency of a branch is unimportant
 250   InstrItinData<IIC_Br      , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 251
 252   // VFP
 253   // Issue through integer pipeline, and execute in NEON unit. We assume
 254   // RunFast mode so that NFP pipeline is used for single-precision when
 255   // possible.
 256   //
 257   // FP Special Register to Integer Register File Move
 258   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 259                               InstrStage<1, [A8_NLSPipe]>], [20]>,
 260   //
 261   // Single-precision FP Unary
 262   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 263                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 264   //
 265   // Double-precision FP Unary
 266   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 267                                InstrStage<4, [A8_NPipe], 0>,
 268                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 269   //
 270   // Single-precision FP Compare
 271   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 272                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 273   //
 274   // Double-precision FP Compare
 275   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 276                                InstrStage<4, [A8_NPipe], 0>,
 277                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 278   //
 279   // Single to Double FP Convert
 280   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 281                                InstrStage<7, [A8_NPipe], 0>,
 282                                InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
 283   //
 284   // Double to Single FP Convert
 285   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 286                                InstrStage<5, [A8_NPipe], 0>,
 287                                InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
 288   //
 289   // Single-Precision FP to Integer Convert
 290   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 291                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 292   //
 293   // Double-Precision FP to Integer Convert
 294   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 295                                InstrStage<8, [A8_NPipe], 0>,
 296                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 297   //
 298   // Integer to Single-Precision FP Convert
 299   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 300                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 301   //
 302   // Integer to Double-Precision FP Convert
 303   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 304                                InstrStage<8, [A8_NPipe], 0>,
 305                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 306   //
 307   // Single-precision FP ALU
 308   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 309                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 310   //
 311   // Double-precision FP ALU
 312   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 313                                InstrStage<9, [A8_NPipe], 0>,
 314                                InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
 315   //
 316   // Single-precision FP Multiply
 317   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 318                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 319   //
 320   // Double-precision FP Multiply
 321   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 322                                InstrStage<11, [A8_NPipe], 0>,
 323                                InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
 324   //
 325   // Single-precision FP MAC
 326   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 327                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 328   //
 329   // Double-precision FP MAC
 330   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 331                                InstrStage<19, [A8_NPipe], 0>,
 332                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 333   //
 334   // Single-precision Fused FP MAC
 335   InstrItinData<IIC_fpFMAC32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 336                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 337   //
 338   // Double-precision Fused FP MAC
 339   InstrItinData<IIC_fpFMAC64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 340                                InstrStage<19, [A8_NPipe], 0>,
 341                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 342   //
 343   // Single-precision FP DIV
 344   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 345                                InstrStage<20, [A8_NPipe], 0>,
 346                                InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
 347   //
 348   // Double-precision FP DIV
 349   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 350                                InstrStage<29, [A8_NPipe], 0>,
 351                                InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
 352   //
 353   // Single-precision FP SQRT
 354   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 355                                InstrStage<19, [A8_NPipe], 0>,
 356                                InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
 357   //
 358   // Double-precision FP SQRT
 359   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 360                                InstrStage<29, [A8_NPipe], 0>,
 361                                InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
 362
 363   //
 364   // Integer to Single-precision Move
 365   InstrItinData<IIC_fpMOVIS,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 366                                InstrStage<1, [A8_NPipe]>],
 367                               [2, 1]>,
 368   //
 369   // Integer to Double-precision Move
 370   InstrItinData<IIC_fpMOVID,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 371                                InstrStage<1, [A8_NPipe]>],
 372                               [2, 1, 1]>,
 373   //
 374   // Single-precision to Integer Move
 375   InstrItinData<IIC_fpMOVSI,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 376                                InstrStage<1, [A8_NPipe]>],
 377                               [20, 1]>,
 378   //
 379   // Double-precision to Integer Move
 380   InstrItinData<IIC_fpMOVDI,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 381                                InstrStage<1, [A8_NPipe]>],
 382                               [20, 20, 1]>,
 383
 384   //
 385   // Single-precision FP Load
 386   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 387                                InstrStage<1, [A8_NLSPipe], 0>,
 388                                InstrStage<1, [A8_LSPipe]>],
 389                               [2, 1]>,
 390   //
 391   // Double-precision FP Load
 392   InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 393                                InstrStage<1, [A8_NLSPipe], 0>,
 394                                InstrStage<1, [A8_LSPipe]>],
 395                               [2, 1]>,
 396   //
 397   // FP Load Multiple
 398   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 399   InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 400                                InstrStage<1, [A8_NLSPipe], 0>,
 401                                InstrStage<1, [A8_LSPipe]>,
 402                                InstrStage<1, [A8_NLSPipe], 0>,
 403                                InstrStage<1, [A8_LSPipe]>],
 404                 [1, 1, 1, 2], [], -1>, // dynamic uops
 405   //
 406   // FP Load Multiple + update
 407   InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 408                                InstrStage<1, [A8_NLSPipe], 0>,
 409                                InstrStage<1, [A8_LSPipe]>,
 410                                InstrStage<1, [A8_NLSPipe], 0>,
 411                                InstrStage<1, [A8_LSPipe]>],
 412                 [2, 1, 1, 1, 2], [], -1>, // dynamic uops
 413   //
 414   // Single-precision FP Store
 415   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 416                                InstrStage<1, [A8_NLSPipe], 0>,
 417                                InstrStage<1, [A8_LSPipe]>],
 418                               [1, 1]>,
 419   //
 420   // Double-precision FP Store
 421   InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 422                                InstrStage<1, [A8_NLSPipe], 0>,
 423                                InstrStage<1, [A8_LSPipe]>],
 424                               [1, 1]>,
 425   //
 426   // FP Store Multiple
 427   InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 428                                InstrStage<1, [A8_NLSPipe], 0>,
 429                                InstrStage<1, [A8_LSPipe]>,
 430                                InstrStage<1, [A8_NLSPipe], 0>,
 431                                InstrStage<1, [A8_LSPipe]>],
 432                 [1, 1, 1, 1], [], -1>, // dynamic uops
 433   //
 434   // FP Store Multiple + update
 435   InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 436                                 InstrStage<1, [A8_NLSPipe], 0>,
 437                                 InstrStage<1, [A8_LSPipe]>,
 438                                 InstrStage<1, [A8_NLSPipe], 0>,
 439                                 InstrStage<1, [A8_LSPipe]>],
 440                 [2, 1, 1, 1, 1], [], -1>, // dynamic uops
 441   // NEON
 442   // Issue through integer pipeline, and execute in NEON unit.
 443   //
 444   // VLD1
 445   InstrItinData<IIC_VLD1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 446                                InstrStage<2, [A8_NLSPipe], 0>,
 447                                InstrStage<2, [A8_LSPipe]>],
 448                               [2, 1]>,
 449   // VLD1x2
 450   InstrItinData<IIC_VLD1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 451                                InstrStage<2, [A8_NLSPipe], 0>,
 452                                InstrStage<2, [A8_LSPipe]>],
 453                               [2, 2, 1]>,
 454   //
 455   // VLD1x3
 456   InstrItinData<IIC_VLD1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 457                                InstrStage<3, [A8_NLSPipe], 0>,
 458                                InstrStage<3, [A8_LSPipe]>],
 459                               [2, 2, 3, 1]>,
 460   //
 461   // VLD1x4
 462   InstrItinData<IIC_VLD1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 463                                InstrStage<3, [A8_NLSPipe], 0>,
 464                                InstrStage<3, [A8_LSPipe]>],
 465                               [2, 2, 3, 3, 1]>,
 466   //
 467   // VLD1u
 468   InstrItinData<IIC_VLD1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 469                                InstrStage<2, [A8_NLSPipe], 0>,
 470                                InstrStage<2, [A8_LSPipe]>],
 471                               [2, 2, 1]>,
 472   //
 473   // VLD1x2u
 474   InstrItinData<IIC_VLD1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 475                                InstrStage<2, [A8_NLSPipe], 0>,
 476                                InstrStage<2, [A8_LSPipe]>],
 477                               [2, 2, 2, 1]>,
 478   //
 479   // VLD1x3u
 480   InstrItinData<IIC_VLD1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 481                                InstrStage<3, [A8_NLSPipe], 0>,
 482                                InstrStage<3, [A8_LSPipe]>],
 483                               [2, 2, 3, 2, 1]>,
 484   //
 485   // VLD1x4u
 486   InstrItinData<IIC_VLD1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 487                                InstrStage<3, [A8_NLSPipe], 0>,
 488                                InstrStage<3, [A8_LSPipe]>],
 489                               [2, 2, 3, 3, 2, 1]>,
 490   //
 491   // VLD1ln
 492   InstrItinData<IIC_VLD1ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 493                                InstrStage<3, [A8_NLSPipe], 0>,
 494                                InstrStage<3, [A8_LSPipe]>],
 495                               [3, 1, 1, 1]>,
 496   //
 497   // VLD1lnu
 498   InstrItinData<IIC_VLD1lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 499                                InstrStage<3, [A8_NLSPipe], 0>,
 500                                InstrStage<3, [A8_LSPipe]>],
 501                               [3, 2, 1, 1, 1, 1]>,
 502   //
 503   // VLD1dup
 504   InstrItinData<IIC_VLD1dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 505                                InstrStage<2, [A8_NLSPipe], 0>,
 506                                InstrStage<2, [A8_LSPipe]>],
 507                               [2, 1]>,
 508   //
 509   // VLD1dupu
 510   InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 511                                InstrStage<2, [A8_NLSPipe], 0>,
 512                                InstrStage<2, [A8_LSPipe]>],
 513                               [2, 2, 1, 1]>,
 514   //
 515   // VLD2
 516   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 517                                InstrStage<2, [A8_NLSPipe], 0>,
 518                                InstrStage<2, [A8_LSPipe]>],
 519                               [2, 2, 1]>,
 520   //
 521   // VLD2x2
 522   InstrItinData<IIC_VLD2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 523                                InstrStage<3, [A8_NLSPipe], 0>,
 524                                InstrStage<3, [A8_LSPipe]>],
 525                               [2, 2, 3, 3, 1]>,
 526   //
 527   // VLD2ln
 528   InstrItinData<IIC_VLD2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 529                                InstrStage<3, [A8_NLSPipe], 0>,
 530                                InstrStage<3, [A8_LSPipe]>],
 531                               [3, 3, 1, 1, 1, 1]>,
 532   //
 533   // VLD2u
 534   InstrItinData<IIC_VLD2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 535                                InstrStage<2, [A8_NLSPipe], 0>,
 536                                InstrStage<2, [A8_LSPipe]>],
 537                               [2, 2, 2, 1, 1, 1]>,
 538   //
 539   // VLD2x2u
 540   InstrItinData<IIC_VLD2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 541                                InstrStage<3, [A8_NLSPipe], 0>,
 542                                InstrStage<3, [A8_LSPipe]>],
 543                               [2, 2, 3, 3, 2, 1]>,
 544   //
 545   // VLD2lnu
 546   InstrItinData<IIC_VLD2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 547                                InstrStage<3, [A8_NLSPipe], 0>,
 548                                InstrStage<3, [A8_LSPipe]>],
 549                               [3, 3, 2, 1, 1, 1, 1, 1]>,
 550   //
 551   // VLD2dup
 552   InstrItinData<IIC_VLD2dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 553                                InstrStage<2, [A8_NLSPipe], 0>,
 554                                InstrStage<2, [A8_LSPipe]>],
 555                               [2, 2, 1]>,
 556   //
 557   // VLD2dupu
 558   InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 559                                InstrStage<2, [A8_NLSPipe], 0>,
 560                                InstrStage<2, [A8_LSPipe]>],
 561                               [2, 2, 2, 1, 1]>,
 562   //
 563   // VLD3
 564   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 565                                InstrStage<4, [A8_NLSPipe], 0>,
 566                                InstrStage<4, [A8_LSPipe]>],
 567                               [3, 3, 4, 1]>,
 568   //
 569   // VLD3ln
 570   InstrItinData<IIC_VLD3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 571                                InstrStage<5, [A8_NLSPipe], 0>,
 572                                InstrStage<5, [A8_LSPipe]>],
 573                               [4, 4, 5, 1, 1, 1, 1, 2]>,
 574   //
 575   // VLD3u
 576   InstrItinData<IIC_VLD3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 577                                InstrStage<4, [A8_NLSPipe], 0>,
 578                                InstrStage<4, [A8_LSPipe]>],
 579                               [3, 3, 4, 2, 1]>,
 580   //
 581   // VLD3lnu
 582   InstrItinData<IIC_VLD3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 583                                InstrStage<5, [A8_NLSPipe], 0>,
 584                                InstrStage<5, [A8_LSPipe]>],
 585                               [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
 586   //
 587   // VLD3dup
 588   InstrItinData<IIC_VLD3dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 589                                InstrStage<3, [A8_NLSPipe], 0>,
 590                                InstrStage<3, [A8_LSPipe]>],
 591                               [2, 2, 3, 1]>,
 592   //
 593   // VLD3dupu
 594   InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 595                                InstrStage<3, [A8_NLSPipe], 0>,
 596                                InstrStage<3, [A8_LSPipe]>],
 597                               [2, 2, 3, 2, 1, 1]>,
 598   //
 599   // VLD4
 600   InstrItinData<IIC_VLD4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 601                                InstrStage<4, [A8_NLSPipe], 0>,
 602                                InstrStage<4, [A8_LSPipe]>],
 603                               [3, 3, 4, 4, 1]>,
 604   //
 605   // VLD4ln
 606   InstrItinData<IIC_VLD4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 607                                InstrStage<5, [A8_NLSPipe], 0>,
 608                                InstrStage<5, [A8_LSPipe]>],
 609                               [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
 610   //
 611   // VLD4u
 612   InstrItinData<IIC_VLD4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 613                                InstrStage<4, [A8_NLSPipe], 0>,
 614                                InstrStage<4, [A8_LSPipe]>],
 615                               [3, 3, 4, 4, 2, 1]>,
 616   //
 617   // VLD4lnu
 618   InstrItinData<IIC_VLD4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 619                                InstrStage<5, [A8_NLSPipe], 0>,
 620                                InstrStage<5, [A8_LSPipe]>],
 621                               [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
 622   //
 623   // VLD4dup
 624   InstrItinData<IIC_VLD4dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 625                                InstrStage<3, [A8_NLSPipe], 0>,
 626                                InstrStage<3, [A8_LSPipe]>],
 627                               [2, 2, 3, 3, 1]>,
 628   //
 629   // VLD4dupu
 630   InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 631                                InstrStage<3, [A8_NLSPipe], 0>,
 632                                InstrStage<3, [A8_LSPipe]>],
 633                               [2, 2, 3, 3, 2, 1, 1]>,
 634   //
 635   // VST1
 636   InstrItinData<IIC_VST1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 637                                InstrStage<2, [A8_NLSPipe], 0>,
 638                                InstrStage<2, [A8_LSPipe]>],
 639                               [1, 1, 1]>,
 640   //
 641   // VST1x2
 642   InstrItinData<IIC_VST1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 643                                InstrStage<2, [A8_NLSPipe], 0>,
 644                                InstrStage<2, [A8_LSPipe]>],
 645                               [1, 1, 1, 1]>,
 646   //
 647   // VST1x3
 648   InstrItinData<IIC_VST1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 649                                InstrStage<3, [A8_NLSPipe], 0>,
 650                                InstrStage<3, [A8_LSPipe]>],
 651                               [1, 1, 1, 1, 2]>,
 652   //
 653   // VST1x4
 654   InstrItinData<IIC_VST1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 655                                InstrStage<3, [A8_NLSPipe], 0>,
 656                                InstrStage<3, [A8_LSPipe]>],
 657                               [1, 1, 1, 1, 2, 2]>,
 658   //
 659   // VST1u
 660   InstrItinData<IIC_VST1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 661                                InstrStage<2, [A8_NLSPipe], 0>,
 662                                InstrStage<2, [A8_LSPipe]>],
 663                               [2, 1, 1, 1, 1]>,
 664   //
 665   // VST1x2u
 666   InstrItinData<IIC_VST1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 667                                InstrStage<2, [A8_NLSPipe], 0>,
 668                                InstrStage<2, [A8_LSPipe]>],
 669                               [2, 1, 1, 1, 1, 1]>,
 670   //
 671   // VST1x3u
 672   InstrItinData<IIC_VST1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 673                                InstrStage<3, [A8_NLSPipe], 0>,
 674                                InstrStage<3, [A8_LSPipe]>],
 675                               [2, 1, 1, 1, 1, 1, 2]>,
 676   //
 677   // VST1x4u
 678   InstrItinData<IIC_VST1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 679                                InstrStage<3, [A8_NLSPipe], 0>,
 680                                InstrStage<3, [A8_LSPipe]>],
 681                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 682   //
 683   // VST1ln
 684   InstrItinData<IIC_VST1ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 685                                InstrStage<2, [A8_NLSPipe], 0>,
 686                                InstrStage<2, [A8_LSPipe]>],
 687                               [1, 1, 1]>,
 688   //
 689   // VST1lnu
 690   InstrItinData<IIC_VST1lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 691                                InstrStage<2, [A8_NLSPipe], 0>,
 692                                InstrStage<2, [A8_LSPipe]>],
 693                               [2, 1, 1, 1, 1]>,
 694   //
 695   // VST2
 696   InstrItinData<IIC_VST2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 697                                InstrStage<2, [A8_NLSPipe], 0>,
 698                                InstrStage<2, [A8_LSPipe]>],
 699                               [1, 1, 1, 1]>,
 700   //
 701   // VST2x2
 702   InstrItinData<IIC_VST2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 703                                InstrStage<4, [A8_NLSPipe], 0>,
 704                                InstrStage<4, [A8_LSPipe]>],
 705                               [1, 1, 1, 1, 2, 2]>,
 706   //
 707   // VST2u
 708   InstrItinData<IIC_VST2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 709                                InstrStage<2, [A8_NLSPipe], 0>,
 710                                InstrStage<2, [A8_LSPipe]>],
 711                               [2, 1, 1, 1, 1, 1]>,
 712   //
 713   // VST2x2u
 714   InstrItinData<IIC_VST2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 715                                InstrStage<4, [A8_NLSPipe], 0>,
 716                                InstrStage<4, [A8_LSPipe]>],
 717                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 718   //
 719   // VST2ln
 720   InstrItinData<IIC_VST2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 721                                InstrStage<2, [A8_NLSPipe], 0>,
 722                                InstrStage<2, [A8_LSPipe]>],
 723                               [1, 1, 1, 1]>,
 724   //
 725   // VST2lnu
 726   InstrItinData<IIC_VST2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 727                                InstrStage<2, [A8_NLSPipe], 0>,
 728                                InstrStage<2, [A8_LSPipe]>],
 729                               [2, 1, 1, 1, 1, 1]>,
 730   //
 731   // VST3
 732   InstrItinData<IIC_VST3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 733                                InstrStage<3, [A8_NLSPipe], 0>,
 734                                InstrStage<3, [A8_LSPipe]>],
 735                               [1, 1, 1, 1, 2]>,
 736   //
 737   // VST3u
 738   InstrItinData<IIC_VST3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 739                                InstrStage<3, [A8_NLSPipe], 0>,
 740                                InstrStage<3, [A8_LSPipe]>],
 741                               [2, 1, 1, 1, 1, 1, 2]>,
 742   //
 743   // VST3ln
 744   InstrItinData<IIC_VST3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 745                                InstrStage<3, [A8_NLSPipe], 0>,
 746                                InstrStage<3, [A8_LSPipe]>],
 747                               [1, 1, 1, 1, 2]>,
 748   //
 749   // VST3lnu
 750   InstrItinData<IIC_VST3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 751                                InstrStage<3, [A8_NLSPipe], 0>,
 752                                InstrStage<3, [A8_LSPipe]>],
 753                               [2, 1, 1, 1, 1, 1, 2]>,
 754   //
 755   // VST4
 756   InstrItinData<IIC_VST4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 757                                InstrStage<4, [A8_NLSPipe], 0>,
 758                                InstrStage<4, [A8_LSPipe]>],
 759                               [1, 1, 1, 1, 2, 2]>,
 760   //
 761   // VST4u
 762   InstrItinData<IIC_VST4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 763                                InstrStage<4, [A8_NLSPipe], 0>,
 764                                InstrStage<4, [A8_LSPipe]>],
 765                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 766   //
 767   // VST4ln
 768   InstrItinData<IIC_VST4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 769                                InstrStage<4, [A8_NLSPipe], 0>,
 770                                InstrStage<4, [A8_LSPipe]>],
 771                               [1, 1, 1, 1, 2, 2]>,
 772   //
 773   // VST4lnu
 774   InstrItinData<IIC_VST4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 775                                InstrStage<4, [A8_NLSPipe], 0>,
 776                                InstrStage<4, [A8_LSPipe]>],
 777                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 778   //
 779   // Double-register FP Unary
 780   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 781                                InstrStage<1, [A8_NPipe]>], [5, 2]>,
 782   //
 783   // Quad-register FP Unary
 784   // Result written in N5, but that is relative to the last cycle of multicycle,
 785   // so we use 6 for those cases
 786   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 787                                InstrStage<2, [A8_NPipe]>], [6, 2]>,
 788   //
 789   // Double-register FP Binary
 790   InstrItinData<IIC_VBIND,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 791                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 792   //
 793   // VPADD, etc.
 794   InstrItinData<IIC_VPBIND,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 795                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 796   //
 797   // Double-register FP VMUL
 798   InstrItinData<IIC_VFMULD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 799                                InstrStage<1, [A8_NPipe]>], [5, 2, 1]>,
 800
 801   //
 802   // Quad-register FP Binary
 803   // Result written in N5, but that is relative to the last cycle of multicycle,
 804   // so we use 6 for those cases
 805   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 806                                InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
 807   //
 808   // Quad-register FP VMUL
 809   InstrItinData<IIC_VFMULQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 810                                InstrStage<1, [A8_NPipe]>], [6, 2, 1]>,
 811   //
 812   // Move
 813   InstrItinData<IIC_VMOV,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 814                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 815   //
 816   // Move Immediate
 817   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 818                                InstrStage<1, [A8_NPipe]>], [3]>,
 819   //
 820   // Double-register Permute Move
 821   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 822                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 823   //
 824   // Quad-register Permute Move
 825   // Result written in N2, but that is relative to the last cycle of multicycle,
 826   // so we use 3 for those cases
 827   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 828                                InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
 829   //
 830   // Integer to Single-precision Move
 831   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 832                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 833   //
 834   // Integer to Double-precision Move
 835   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 836                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 837   //
 838   // Single-precision to Integer Move
 839   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 840                                InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
 841   //
 842   // Double-precision to Integer Move
 843   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 844                                InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
 845   //
 846   // Integer to Lane Move
 847   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 848                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 849   //
 850   // Vector narrow move
 851   InstrItinData<IIC_VMOVN   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 852                                InstrStage<1, [A8_NPipe]>], [2, 1]>,
 853   //
 854   // Double-register Permute
 855   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 856                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
 857   //
 858   // Quad-register Permute
 859   // Result written in N2, but that is relative to the last cycle of multicycle,
 860   // so we use 3 for those cases
 861   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 862                                InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
 863   //
 864   // Quad-register Permute (3 cycle issue)
 865   // Result written in N2, but that is relative to the last cycle of multicycle,
 866   // so we use 4 for those cases
 867   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 868                                InstrStage<1, [A8_NLSPipe]>,
 869                                InstrStage<1, [A8_NPipe], 0>,
 870                                InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
 871   //
 872   // Double-register FP Multiple-Accumulate
 873   InstrItinData<IIC_VMACD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 874                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 875   //
 876   // Quad-register FP Multiple-Accumulate
 877   // Result written in N9, but that is relative to the last cycle of multicycle,
 878   // so we use 10 for those cases
 879   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 880                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 881   //
 882   // Double-register Fused FP Multiple-Accumulate
 883   InstrItinData<IIC_VFMACD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 884                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 885   //
 886   // Quad-register Fused FP Multiple-Accumulate
 887   // Result written in N9, but that is relative to the last cycle of multicycle,
 888   // so we use 10 for those cases
 889   InstrItinData<IIC_VFMACQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 890                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 891   //
 892   // Double-register Reciprical Step
 893   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 894                                InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
 895   //
 896   // Quad-register Reciprical Step
 897   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 898                                InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
 899   //
 900   // Double-register Integer Count
 901   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 902                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 903   //
 904   // Quad-register Integer Count
 905   // Result written in N3, but that is relative to the last cycle of multicycle,
 906   // so we use 4 for those cases
 907   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 908                                InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
 909   //
 910   // Double-register Integer Unary
 911   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 912                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 913   //
 914   // Quad-register Integer Unary
 915   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 916                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 917   //
 918   // Double-register Integer Q-Unary
 919   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 920                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 921   //
 922   // Quad-register Integer CountQ-Unary
 923   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 924                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 925   //
 926   // Double-register Integer Binary
 927   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 928                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 929   //
 930   // Quad-register Integer Binary
 931   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 932                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 933   //
 934   // Double-register Integer Binary (4 cycle)
 935   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 936                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 937   //
 938   // Quad-register Integer Binary (4 cycle)
 939   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 940                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 941
 942   //
 943   // Double-register Integer Subtract
 944   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 945                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 946   //
 947   // Quad-register Integer Subtract
 948   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 949                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 950   //
 951   // Double-register Integer Subtract
 952   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 953                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 954   //
 955   // Quad-register Integer Subtract
 956   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 957                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 958   //
 959   // Double-register Integer Shift
 960   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 961                                InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
 962   //
 963   // Quad-register Integer Shift
 964   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 965                                InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
 966   //
 967   // Double-register Integer Shift (4 cycle)
 968   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 969                                InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
 970   //
 971   // Quad-register Integer Shift (4 cycle)
 972   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 973                                InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
 974   //
 975   // Double-register Integer Pair Add Long
 976   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 977                                InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
 978   //
 979   // Quad-register Integer Pair Add Long
 980   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 981                                InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
 982   //
 983   // Double-register Absolute Difference and Accumulate
 984   InstrItinData<IIC_VABAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 985                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
 986   //
 987   // Quad-register Absolute Difference and Accumulate
 988   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 989                                InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
 990
 991   //
 992   // Double-register Integer Multiply (.8, .16)
 993   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 994                                InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
 995   //
 996   // Double-register Integer Multiply (.32)
 997   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 998                                InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
 999   //
1000   // Quad-register Integer Multiply (.8, .16)
1001   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1002                                InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
1003   //
1004   // Quad-register Integer Multiply (.32)
1005   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1006                                InstrStage<1, [A8_NPipe]>,
1007                                InstrStage<2, [A8_NLSPipe], 0>,
1008                                InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
1009   //
1010   // Double-register Integer Multiply-Accumulate (.8, .16)
1011   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1012                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
1013   //
1014   // Double-register Integer Multiply-Accumulate (.32)
1015   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1016                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
1017   //
1018   // Quad-register Integer Multiply-Accumulate (.8, .16)
1019   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1020                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
1021   //
1022   // Quad-register Integer Multiply-Accumulate (.32)
1023   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1024                                InstrStage<1, [A8_NPipe]>,
1025                                InstrStage<2, [A8_NLSPipe], 0>,
1026                                InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
1027   //
1028   // Double-register VEXT
1029   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1030                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
1031   //
1032   // Quad-register VEXT
1033   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1034                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
1035   //
1036   // VTB
1037   InstrItinData<IIC_VTB1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1038                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
1039   InstrItinData<IIC_VTB2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1040                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
1041   InstrItinData<IIC_VTB3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1042                                InstrStage<1, [A8_NLSPipe]>,
1043                                InstrStage<1, [A8_NPipe], 0>,
1044                                InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
1045   InstrItinData<IIC_VTB4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1046                                InstrStage<1, [A8_NLSPipe]>,
1047                                InstrStage<1, [A8_NPipe], 0>,
1048                                InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
1049   //
1050   // VTBX
1051   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1052                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
1053   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1054                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
1055   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1056                                InstrStage<1, [A8_NLSPipe]>,
1057                                InstrStage<1, [A8_NPipe], 0>,
1058                                InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
1059   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1060                                InstrStage<1, [A8_NLSPipe]>,
1061                                InstrStage<1, [A8_NPipe], 0>,
1062                             InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
1063 ]>;