lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 // Functional Units.
  17 def A8_Issue   : FuncUnit; // issue
  18 def A8_Pipe0   : FuncUnit; // pipeline 0
  19 def A8_Pipe1   : FuncUnit; // pipeline 1
  20 def A8_LdSt0   : FuncUnit; // pipeline 0 load/store
  21 def A8_LdSt1   : FuncUnit; // pipeline 1 load/store
  22 def A8_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  23 def A8_NLSPipe : FuncUnit; // NEON LS pipe
  24 //
  25 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
  26 //
  27 def CortexA8Itineraries : ProcessorItineraries<
  28   [A8_Issue, A8_Pipe0, A8_Pipe1, A8_LdSt0, A8_LdSt1, A8_NPipe, A8_NLSPipe],
  29   [], [
  30   // Two fully-pipelined integer ALU pipelines
  31   //
  32   // No operand cycles
  33   InstrItinData<IIC_iALUx    , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
  34   //
  35   // Binary Instructions that produce a result
  36   InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  37   InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  38   InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  39   InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  40   //
  41   // Bitwise Instructions that produce a result
  42   InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  43   InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  44   InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  45   InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  46   //
  47   // Unary Instructions that produce a result
  48   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  49   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  50   //
  51   // Zero and sign extension instructions
  52   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  53   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  54   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
  55   //
  56   // Compare instructions
  57   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  58   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  59   InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  60   InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  61   //
  62   // Move instructions, unconditional
  63   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  64   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  65                              InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  66   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  67   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  68   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  69   //
  70   // Move instructions, conditional
  71   InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  72   InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  73   InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  74   InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  75
  76   // Integer multiply pipeline
  77   // Result written in E5, but that is relative to the last cycle of multicycle,
  78   // so we use 6 for those cases
  79   //
  80   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
  81   InstrItinData<IIC_iMAC16   , [InstrStage<1, [A8_Pipe1], 0>,
  82                                 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  83   InstrItinData<IIC_iMUL32   , [InstrStage<1, [A8_Pipe1], 0>,
  84                                 InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
  85   InstrItinData<IIC_iMAC32   , [InstrStage<1, [A8_Pipe1], 0>,
  86                                 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  87   InstrItinData<IIC_iMUL64   , [InstrStage<2, [A8_Pipe1], 0>,
  88                                 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  89   InstrItinData<IIC_iMAC64   , [InstrStage<2, [A8_Pipe1], 0>,
  90                                 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  91
  92   // Integer load pipeline
  93   //
  94   // loads have an extra cycle of latency, but are fully pipelined
  95   // use A8_Issue to enforce the 1 load/store per cycle limit
  96   //
  97   // Immediate offset
  98   InstrItinData<IIC_iLoadi   , [InstrStage<1, [A8_Issue], 0>,
  99                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 100                                 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
 101   //
 102   // Register offset
 103   InstrItinData<IIC_iLoadr   , [InstrStage<1, [A8_Issue], 0>,
 104                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 105                                 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 106   //
 107   // Scaled register offset, issues over 2 cycles
 108   InstrItinData<IIC_iLoadsi  , [InstrStage<2, [A8_Issue], 0>,
 109                                 InstrStage<1, [A8_Pipe0], 0>,
 110                                 InstrStage<1, [A8_Pipe1]>,
 111                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 112                                 InstrStage<1, [A8_LdSt0]>], [4, 1, 1]>,
 113   //
 114   // Immediate offset with update
 115   InstrItinData<IIC_iLoadiu  , [InstrStage<1, [A8_Issue], 0>,
 116                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 117                                 InstrStage<1, [A8_LdSt0]>], [3, 2, 1]>,
 118   //
 119   // Register offset with update
 120   InstrItinData<IIC_iLoadru  , [InstrStage<1, [A8_Issue], 0>,
 121                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 122                                 InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
 123   //
 124   // Scaled register offset with update, issues over 2 cycles
 125   InstrItinData<IIC_iLoadsiu , [InstrStage<2, [A8_Issue], 0>,
 126                                 InstrStage<1, [A8_Pipe0], 0>,
 127                                 InstrStage<1, [A8_Pipe1]>,
 128                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 129                                 InstrStage<1, [A8_LdSt0]>], [4, 3, 1, 1]>,
 130   //
 131   // Load multiple
 132   InstrItinData<IIC_iLoadm   , [InstrStage<2, [A8_Issue], 0>,
 133                                 InstrStage<2, [A8_Pipe0], 0>,
 134                                 InstrStage<2, [A8_Pipe1]>,
 135                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 136                                 InstrStage<1, [A8_LdSt0]>]>,
 137
 138   //
 139   // Load multiple plus branch
 140   InstrItinData<IIC_iLoadmBr , [InstrStage<2, [A8_Issue], 0>,
 141                                 InstrStage<2, [A8_Pipe0], 0>,
 142                                 InstrStage<2, [A8_Pipe1]>,
 143                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 144                                 InstrStage<1, [A8_LdSt0]>,
 145                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 146
 147   //
 148   // iLoadi + iALUr for t2LDRpci_pic.
 149   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Issue], 0>,
 150                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 151                                 InstrStage<1, [A8_LdSt0]>,
 152                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
 153
 154
 155   // Integer store pipeline
 156   //
 157   // use A8_Issue to enforce the 1 load/store per cycle limit
 158   //
 159   // Immediate offset
 160   InstrItinData<IIC_iStorei  , [InstrStage<1, [A8_Issue], 0>,
 161                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 162                                 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
 163   //
 164   // Register offset
 165   InstrItinData<IIC_iStorer  , [InstrStage<1, [A8_Issue], 0>,
 166                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 167                                 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 168   //
 169   // Scaled register offset, issues over 2 cycles
 170   InstrItinData<IIC_iStoresi , [InstrStage<2, [A8_Issue], 0>,
 171                                 InstrStage<1, [A8_Pipe0], 0>,
 172                                 InstrStage<1, [A8_Pipe1]>,
 173                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 174                                 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 175   //
 176   // Immediate offset with update
 177   InstrItinData<IIC_iStoreiu , [InstrStage<1, [A8_Issue], 0>,
 178                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 179                                 InstrStage<1, [A8_LdSt0]>], [2, 3, 1]>,
 180   //
 181   // Register offset with update
 182   InstrItinData<IIC_iStoreru  , [InstrStage<1, [A8_Issue], 0>,
 183                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 184                                 InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
 185   //
 186   // Scaled register offset with update, issues over 2 cycles
 187   InstrItinData<IIC_iStoresiu, [InstrStage<2, [A8_Issue], 0>,
 188                                 InstrStage<1, [A8_Pipe0], 0>,
 189                                 InstrStage<1, [A8_Pipe1]>,
 190                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 191                                 InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>,
 192   //
 193   // Store multiple
 194   InstrItinData<IIC_iStorem  , [InstrStage<2, [A8_Issue], 0>,
 195                                 InstrStage<2, [A8_Pipe0], 0>,
 196                                 InstrStage<2, [A8_Pipe1]>,
 197                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 198                                 InstrStage<1, [A8_LdSt0]>]>,
 199
 200   // Branch
 201   //
 202   // no delay slots, so the latency of a branch is unimportant
 203   InstrItinData<IIC_Br      , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 204
 205   // VFP
 206   // Issue through integer pipeline, and execute in NEON unit. We assume
 207   // RunFast mode so that NFP pipeline is used for single-precision when
 208   // possible.
 209   //
 210   // FP Special Register to Integer Register File Move
 211   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 212                               InstrStage<1, [A8_NLSPipe]>]>,
 213   //
 214   // Single-precision FP Unary
 215   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 216                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 217   //
 218   // Double-precision FP Unary
 219   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 220                                InstrStage<4, [A8_NPipe], 0>,
 221                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 222   //
 223   // Single-precision FP Compare
 224   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 225                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 226   //
 227   // Double-precision FP Compare
 228   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 229                                InstrStage<4, [A8_NPipe], 0>,
 230                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 231   //
 232   // Single to Double FP Convert
 233   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 234                                InstrStage<7, [A8_NPipe], 0>,
 235                                InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
 236   //
 237   // Double to Single FP Convert
 238   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 239                                InstrStage<5, [A8_NPipe], 0>,
 240                                InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
 241   //
 242   // Single-Precision FP to Integer Convert
 243   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 244                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 245   //
 246   // Double-Precision FP to Integer Convert
 247   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 248                                InstrStage<8, [A8_NPipe], 0>,
 249                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 250   //
 251   // Integer to Single-Precision FP Convert
 252   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 253                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 254   //
 255   // Integer to Double-Precision FP Convert
 256   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 257                                InstrStage<8, [A8_NPipe], 0>,
 258                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 259   //
 260   // Single-precision FP ALU
 261   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 262                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 263   //
 264   // Double-precision FP ALU
 265   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 266                                InstrStage<9, [A8_NPipe], 0>,
 267                                InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
 268   //
 269   // Single-precision FP Multiply
 270   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 271                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 272   //
 273   // Double-precision FP Multiply
 274   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 275                                InstrStage<11, [A8_NPipe], 0>,
 276                                InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
 277   //
 278   // Single-precision FP MAC
 279   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 280                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 281   //
 282   // Double-precision FP MAC
 283   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 284                                InstrStage<19, [A8_NPipe], 0>,
 285                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 286   //
 287   // Single-precision FP DIV
 288   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 289                                InstrStage<20, [A8_NPipe], 0>,
 290                                InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
 291   //
 292   // Double-precision FP DIV
 293   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 294                                InstrStage<29, [A8_NPipe], 0>,
 295                                InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
 296   //
 297   // Single-precision FP SQRT
 298   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 299                                InstrStage<19, [A8_NPipe], 0>,
 300                                InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
 301   //
 302   // Double-precision FP SQRT
 303   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 304                                InstrStage<29, [A8_NPipe], 0>,
 305                                InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
 306   //
 307   // Single-precision FP Load
 308   // use A8_Issue to enforce the 1 load/store per cycle limit
 309   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>,
 310                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 311                                InstrStage<1, [A8_LdSt0], 0>,
 312                                InstrStage<1, [A8_NLSPipe]>]>,
 313   //
 314   // Double-precision FP Load
 315   // use A8_Issue to enforce the 1 load/store per cycle limit
 316   InstrItinData<IIC_fpLoad64, [InstrStage<2, [A8_Issue], 0>,
 317                                InstrStage<1, [A8_Pipe0], 0>,
 318                                InstrStage<1, [A8_Pipe1]>,
 319                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 320                                InstrStage<1, [A8_LdSt0], 0>,
 321                                InstrStage<1, [A8_NLSPipe]>]>,
 322   //
 323   // FP Load Multiple
 324   // use A8_Issue to enforce the 1 load/store per cycle limit
 325   InstrItinData<IIC_fpLoadm,  [InstrStage<3, [A8_Issue], 0>,
 326                                InstrStage<2, [A8_Pipe0], 0>,
 327                                InstrStage<2, [A8_Pipe1]>,
 328                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 329                                InstrStage<1, [A8_LdSt0], 0>,
 330                                InstrStage<1, [A8_NLSPipe]>]>,
 331   //
 332   // Single-precision FP Store
 333   // use A8_Issue to enforce the 1 load/store per cycle limit
 334   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>,
 335                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 336                                InstrStage<1, [A8_LdSt0], 0>,
 337                                InstrStage<1, [A8_NLSPipe]>]>,
 338   //
 339   // Double-precision FP Store
 340   // use A8_Issue to enforce the 1 load/store per cycle limit
 341   InstrItinData<IIC_fpStore64,[InstrStage<2, [A8_Issue], 0>,
 342                                InstrStage<1, [A8_Pipe0], 0>,
 343                                InstrStage<1, [A8_Pipe1]>,
 344                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 345                                InstrStage<1, [A8_LdSt0], 0>,
 346                                InstrStage<1, [A8_NLSPipe]>]>,
 347   //
 348   // FP Store Multiple
 349   // use A8_Issue to enforce the 1 load/store per cycle limit
 350   InstrItinData<IIC_fpStorem, [InstrStage<3, [A8_Issue], 0>,
 351                                InstrStage<2, [A8_Pipe0], 0>,
 352                                InstrStage<2, [A8_Pipe1]>,
 353                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 354                                InstrStage<1, [A8_LdSt0], 0>,
 355                                InstrStage<1, [A8_NLSPipe]>]>,
 356
 357   // NEON
 358   // Issue through integer pipeline, and execute in NEON unit.
 359   //
 360   // VLD1
 361   // FIXME: We don't model this instruction properly
 362   InstrItinData<IIC_VLD1,     [InstrStage<1, [A8_Issue], 0>,
 363                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 364                                InstrStage<1, [A8_LdSt0], 0>,
 365                                InstrStage<1, [A8_NLSPipe]>]>,
 366   //
 367   // VLD2
 368   // FIXME: We don't model this instruction properly
 369   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Issue], 0>,
 370                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 371                                InstrStage<1, [A8_LdSt0], 0>,
 372                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1]>,
 373   //
 374   // VLD3
 375   // FIXME: We don't model this instruction properly
 376   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Issue], 0>,
 377                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 378                                InstrStage<1, [A8_LdSt0], 0>,
 379                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 1]>,
 380   //
 381   // VLD4
 382   // FIXME: We don't model this instruction properly
 383   InstrItinData<IIC_VLD4,     [InstrStage<1, [A8_Issue], 0>,
 384                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 385                                InstrStage<1, [A8_LdSt0], 0>,
 386                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 2, 1]>,
 387   //
 388   // VST
 389   // FIXME: We don't model this instruction properly
 390   InstrItinData<IIC_VST,      [InstrStage<1, [A8_Issue], 0>,
 391                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 392                                InstrStage<1, [A8_LdSt0], 0>,
 393                                InstrStage<1, [A8_NLSPipe]>]>,
 394   //
 395   // Double-register FP Unary
 396   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 397                                InstrStage<1, [A8_NPipe]>], [5, 2]>,
 398   //
 399   // Quad-register FP Unary
 400   // Result written in N5, but that is relative to the last cycle of multicycle,
 401   // so we use 6 for those cases
 402   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 403                                InstrStage<2, [A8_NPipe]>], [6, 2]>,
 404   //
 405   // Double-register FP Binary
 406   InstrItinData<IIC_VBIND,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 407                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 408   //
 409   // Quad-register FP Binary
 410   // Result written in N5, but that is relative to the last cycle of multicycle,
 411   // so we use 6 for those cases
 412   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 413                                InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
 414   //
 415   // Move Immediate
 416   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 417                                InstrStage<1, [A8_NPipe]>], [3]>,
 418   //
 419   // Double-register Permute Move
 420   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 421                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 422   //
 423   // Quad-register Permute Move
 424   // Result written in N2, but that is relative to the last cycle of multicycle,
 425   // so we use 3 for those cases
 426   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 427                                InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
 428   //
 429   // Integer to Single-precision Move
 430   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 431                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 432   //
 433   // Integer to Double-precision Move
 434   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 435                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 436   //
 437   // Single-precision to Integer Move
 438   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 439                                InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
 440   //
 441   // Double-precision to Integer Move
 442   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 443                                InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
 444   //
 445   // Integer to Lane Move
 446   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 447                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 448   //
 449   // Double-register Permute
 450   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 451                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
 452   //
 453   // Quad-register Permute
 454   // Result written in N2, but that is relative to the last cycle of multicycle,
 455   // so we use 3 for those cases
 456   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 457                                InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
 458   //
 459   // Quad-register Permute (3 cycle issue)
 460   // Result written in N2, but that is relative to the last cycle of multicycle,
 461   // so we use 4 for those cases
 462   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 463                                InstrStage<1, [A8_NLSPipe]>,
 464                                InstrStage<1, [A8_NPipe], 0>,
 465                                InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
 466   //
 467   // Double-register FP Multiple-Accumulate
 468   InstrItinData<IIC_VMACD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 469                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 470   //
 471   // Quad-register FP Multiple-Accumulate
 472   // Result written in N9, but that is relative to the last cycle of multicycle,
 473   // so we use 10 for those cases
 474   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 475                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 476   //
 477   // Double-register Reciprical Step
 478   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 479                                InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
 480   //
 481   // Quad-register Reciprical Step
 482   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 483                                InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
 484   //
 485   // Double-register Integer Count
 486   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 487                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 488   //
 489   // Quad-register Integer Count
 490   // Result written in N3, but that is relative to the last cycle of multicycle,
 491   // so we use 4 for those cases
 492   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 493                                InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
 494   //
 495   // Double-register Integer Unary
 496   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 497                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 498   //
 499   // Quad-register Integer Unary
 500   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 501                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 502   //
 503   // Double-register Integer Q-Unary
 504   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 505                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 506   //
 507   // Quad-register Integer CountQ-Unary
 508   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 509                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 510   //
 511   // Double-register Integer Binary
 512   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 513                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 514   //
 515   // Quad-register Integer Binary
 516   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 517                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 518   //
 519   // Double-register Integer Binary (4 cycle)
 520   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 521                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 522   //
 523   // Quad-register Integer Binary (4 cycle)
 524   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 525                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 526
 527   //
 528   // Double-register Integer Subtract
 529   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 530                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 531   //
 532   // Quad-register Integer Subtract
 533   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 534                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 535   //
 536   // Double-register Integer Subtract
 537   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 538                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 539   //
 540   // Quad-register Integer Subtract
 541   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 542                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 543   //
 544   // Double-register Integer Shift
 545   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 546                                InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
 547   //
 548   // Quad-register Integer Shift
 549   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 550                                InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
 551   //
 552   // Double-register Integer Shift (4 cycle)
 553   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 554                                InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
 555   //
 556   // Quad-register Integer Shift (4 cycle)
 557   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 558                                InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
 559   //
 560   // Double-register Integer Pair Add Long
 561   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 562                                InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
 563   //
 564   // Quad-register Integer Pair Add Long
 565   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 566                                InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
 567   //
 568   // Double-register Absolute Difference and Accumulate
 569   InstrItinData<IIC_VABAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 570                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
 571   //
 572   // Quad-register Absolute Difference and Accumulate
 573   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 574                                InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
 575
 576   //
 577   // Double-register Integer Multiply (.8, .16)
 578   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 579                                InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
 580   //
 581   // Double-register Integer Multiply (.32)
 582   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 583                                InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
 584   //
 585   // Quad-register Integer Multiply (.8, .16)
 586   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 587                                InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
 588   //
 589   // Quad-register Integer Multiply (.32)
 590   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 591                                InstrStage<1, [A8_NPipe]>,
 592                                InstrStage<2, [A8_NLSPipe], 0>,
 593                                InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
 594   //
 595   // Double-register Integer Multiply-Accumulate (.8, .16)
 596   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 597                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
 598   //
 599   // Double-register Integer Multiply-Accumulate (.32)
 600   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 601                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
 602   //
 603   // Quad-register Integer Multiply-Accumulate (.8, .16)
 604   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 605                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
 606   //
 607   // Quad-register Integer Multiply-Accumulate (.32)
 608   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 609                                InstrStage<1, [A8_NPipe]>,
 610                                InstrStage<2, [A8_NLSPipe], 0>,
 611                                InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
 612   //
 613   // Double-register VEXT
 614   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 615                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 616   //
 617   // Quad-register VEXT
 618   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 619                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 620   //
 621   // VTB
 622   InstrItinData<IIC_VTB1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 623                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
 624   InstrItinData<IIC_VTB2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 625                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
 626   InstrItinData<IIC_VTB3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 627                                InstrStage<1, [A8_NLSPipe]>,
 628                                InstrStage<1, [A8_NPipe], 0>,
 629                                InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
 630   InstrItinData<IIC_VTB4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 631                                InstrStage<1, [A8_NLSPipe]>,
 632                                InstrStage<1, [A8_NPipe], 0>,
 633                                InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
 634   //
 635   // VTBX
 636   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 637                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
 638   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 639                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
 640   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 641                                InstrStage<1, [A8_NLSPipe]>,
 642                                InstrStage<1, [A8_NPipe], 0>,
 643                                InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
 644   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 645                                InstrStage<1, [A8_NLSPipe]>,
 646                                InstrStage<1, [A8_NPipe], 0>,
 647                             InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 648 ]>;