lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 // Functional Units.
  17 def A8_Pipe0   : FuncUnit; // pipeline 0
  18 def A8_Pipe1   : FuncUnit; // pipeline 1
  19 def A8_LSPipe  : FuncUnit; // Load / store pipeline
  20 def A8_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
  22 //
  23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
  24 //
  25 def CortexA8Itineraries : ProcessorItineraries<
  26   [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
  27   [], [
  28   // Two fully-pipelined integer ALU pipelines
  29   //
  30   // No operand cycles
  31   InstrItinData<IIC_iALUx    , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
  32   //
  33   // Binary Instructions that produce a result
  34   InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  35   InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  36   InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  37   InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
  38   InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  39   //
  40   // Bitwise Instructions that produce a result
  41   InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  42   InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  43   InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  44   InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  45   //
  46   // Unary Instructions that produce a result
  47   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  48   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  49   //
  50   // Zero and sign extension instructions
  51   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  52   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  53   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
  54   //
  55   // Compare instructions
  56   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  57   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  58   InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  59   InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  60   //
  61   // Test instructions
  62   InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  63   InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  64   InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  65   InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  66   //
  67   // Move instructions, unconditional
  68   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  69   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  70   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  71   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  72   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  73                              InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  74   //
  75   // Move instructions, conditional
  76   InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  77   InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  78   InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  79   InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  80   InstrItinData<IIC_iCMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  81                               InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3, 1]>,
  82   //
  83   // MVN instructions
  84   InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  85   InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  86   InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  87   InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  88
  89   // Integer multiply pipeline
  90   // Result written in E5, but that is relative to the last cycle of multicycle,
  91   // so we use 6 for those cases
  92   //
  93   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
  94   InstrItinData<IIC_iMAC16   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  95   InstrItinData<IIC_iMUL32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
  96   InstrItinData<IIC_iMAC32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  97   InstrItinData<IIC_iMUL64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  98   InstrItinData<IIC_iMAC64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  99
 100   // Integer load pipeline
 101   //
 102   // Immediate offset
 103   InstrItinData<IIC_iLoad_i   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 104                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 105   InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 106                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 107   InstrItinData<IIC_iLoad_d_i,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 108                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 109   //
 110   // Register offset
 111   InstrItinData<IIC_iLoad_r   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 112                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 113   InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 114                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 115   InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 116                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 117   //
 118   // Scaled register offset, issues over 2 cycles
 119   // FIXME: lsl by 2 takes 1 cycle.
 120   InstrItinData<IIC_iLoad_si  , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 121                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 122   InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 123                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 124   //
 125   // Immediate offset with update
 126   InstrItinData<IIC_iLoad_iu  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 127                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 128   InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 129                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 130   //
 131   // Register offset with update
 132   InstrItinData<IIC_iLoad_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 133                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 134   InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 135                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 136   InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 137                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 138   //
 139   // Scaled register offset with update, issues over 2 cycles
 140   InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 141                                  InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
 142   InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 143                                   InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
 144   //
 145   // Load multiple, def is the 5th operand. Pipeline 0 only.
 146   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 147   InstrItinData<IIC_iLoad_m  , [InstrStage<2, [A8_Pipe0], 0>,
 148                                 InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
 149   //
 150   // Load multiple + update, defs are the 1st and 5th operands.
 151   InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>,
 152                                 InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
 153   //
 154   // Load multiple plus branch
 155   InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>,
 156                                 InstrStage<3, [A8_LSPipe]>,
 157                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 158                                [1, 2, 1, 1, 3]>,
 159   //
 160   // Pop, def is the 3rd operand.
 161   InstrItinData<IIC_iPop  ,    [InstrStage<3, [A8_Pipe0], 0>,
 162                                 InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
 163   //
 164   // Push, def is the 3th operand.
 165   InstrItinData<IIC_iPop_Br,   [InstrStage<3, [A8_Pipe0], 0>,
 166                                 InstrStage<3, [A8_LSPipe]>,
 167                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 168                                [1, 1, 3]>,
 169
 170   //
 171   // iLoadi + iALUr for t2LDRpci_pic.
 172   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 173                                 InstrStage<1, [A8_LSPipe]>,
 174                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
 175
 176
 177   // Integer store pipeline
 178   //
 179   // Immediate offset
 180   InstrItinData<IIC_iStore_i  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 181                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 182   InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 183                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 184   InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 185                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 186   //
 187   // Register offset
 188   InstrItinData<IIC_iStore_r  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 189                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 190   InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 191                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 192   InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 193                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 194   //
 195   // Scaled register offset, issues over 2 cycles
 196   InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 197                                  InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 198   InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 199                                   InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 200   //
 201   // Immediate offset with update
 202   InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 203                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 204   InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 205                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 206   //
 207   // Register offset with update
 208   InstrItinData<IIC_iStore_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 209                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 210   InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 211                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 212   InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 213                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 214   //
 215   // Scaled register offset with update, issues over 2 cycles
 216   InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 217                                  InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 218   InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 219                                    InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 220   //
 221   // Store multiple. Pipeline 0 only.
 222   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 223   InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>,
 224                                 InstrStage<2, [A8_LSPipe]>]>,
 225   //
 226   // Store multiple + update
 227   InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>,
 228                                 InstrStage<2, [A8_LSPipe]>], [2]>,
 229
 230   //
 231   // Preload
 232   InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
 233
 234   // Branch
 235   //
 236   // no delay slots, so the latency of a branch is unimportant
 237   InstrItinData<IIC_Br      , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 238
 239   // VFP
 240   // Issue through integer pipeline, and execute in NEON unit. We assume
 241   // RunFast mode so that NFP pipeline is used for single-precision when
 242   // possible.
 243   //
 244   // FP Special Register to Integer Register File Move
 245   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 246                               InstrStage<1, [A8_NLSPipe]>], [20]>,
 247   //
 248   // Single-precision FP Unary
 249   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 250                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 251   //
 252   // Double-precision FP Unary
 253   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 254                                InstrStage<4, [A8_NPipe], 0>,
 255                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 256   //
 257   // Single-precision FP Compare
 258   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 259                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 260   //
 261   // Double-precision FP Compare
 262   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 263                                InstrStage<4, [A8_NPipe], 0>,
 264                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 265   //
 266   // Single to Double FP Convert
 267   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 268                                InstrStage<7, [A8_NPipe], 0>,
 269                                InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
 270   //
 271   // Double to Single FP Convert
 272   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 273                                InstrStage<5, [A8_NPipe], 0>,
 274                                InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
 275   //
 276   // Single-Precision FP to Integer Convert
 277   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 278                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 279   //
 280   // Double-Precision FP to Integer Convert
 281   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 282                                InstrStage<8, [A8_NPipe], 0>,
 283                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 284   //
 285   // Integer to Single-Precision FP Convert
 286   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 287                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 288   //
 289   // Integer to Double-Precision FP Convert
 290   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 291                                InstrStage<8, [A8_NPipe], 0>,
 292                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 293   //
 294   // Single-precision FP ALU
 295   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 296                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 297   //
 298   // Double-precision FP ALU
 299   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 300                                InstrStage<9, [A8_NPipe], 0>,
 301                                InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
 302   //
 303   // Single-precision FP Multiply
 304   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 305                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 306   //
 307   // Double-precision FP Multiply
 308   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 309                                InstrStage<11, [A8_NPipe], 0>,
 310                                InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
 311   //
 312   // Single-precision FP MAC
 313   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 314                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 315   //
 316   // Double-precision FP MAC
 317   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 318                                InstrStage<19, [A8_NPipe], 0>,
 319                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 320   //
 321   // Single-precision FP DIV
 322   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 323                                InstrStage<20, [A8_NPipe], 0>,
 324                                InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
 325   //
 326   // Double-precision FP DIV
 327   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 328                                InstrStage<29, [A8_NPipe], 0>,
 329                                InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
 330   //
 331   // Single-precision FP SQRT
 332   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 333                                InstrStage<19, [A8_NPipe], 0>,
 334                                InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
 335   //
 336   // Double-precision FP SQRT
 337   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 338                                InstrStage<29, [A8_NPipe], 0>,
 339                                InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
 340
 341   //
 342   // Integer to Single-precision Move
 343   InstrItinData<IIC_fpMOVIS,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 344                                InstrStage<1, [A8_NPipe]>],
 345                               [2, 1]>,
 346   //
 347   // Integer to Double-precision Move
 348   InstrItinData<IIC_fpMOVID,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 349                                InstrStage<1, [A8_NPipe]>],
 350                               [2, 1, 1]>,
 351   //
 352   // Single-precision to Integer Move
 353   InstrItinData<IIC_fpMOVSI,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 354                                InstrStage<1, [A8_NPipe]>],
 355                               [20, 1]>,
 356   //
 357   // Double-precision to Integer Move
 358   InstrItinData<IIC_fpMOVDI,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 359                                InstrStage<1, [A8_NPipe]>],
 360                               [20, 20, 1]>,
 361
 362   //
 363   // Single-precision FP Load
 364   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 365                                InstrStage<1, [A8_NLSPipe], 0>,
 366                                InstrStage<1, [A8_LSPipe]>],
 367                               [2, 1]>,
 368   //
 369   // Double-precision FP Load
 370   InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 371                                InstrStage<1, [A8_NLSPipe], 0>,
 372                                InstrStage<1, [A8_LSPipe]>],
 373                               [2, 1]>,
 374   //
 375   // FP Load Multiple
 376   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 377   InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 378                                InstrStage<1, [A8_NLSPipe], 0>,
 379                                InstrStage<1, [A8_LSPipe]>,
 380                                InstrStage<1, [A8_NLSPipe], 0>,
 381                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
 382   //
 383   // FP Load Multiple + update
 384   InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 385                                InstrStage<1, [A8_NLSPipe], 0>,
 386                                InstrStage<1, [A8_LSPipe]>,
 387                                InstrStage<1, [A8_NLSPipe], 0>,
 388                                InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
 389   //
 390   // Single-precision FP Store
 391   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 392                                InstrStage<1, [A8_NLSPipe], 0>,
 393                                InstrStage<1, [A8_LSPipe]>],
 394                               [1, 1]>,
 395   //
 396   // Double-precision FP Store
 397   InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 398                                InstrStage<1, [A8_NLSPipe], 0>,
 399                                InstrStage<1, [A8_LSPipe]>],
 400                               [1, 1]>,
 401   //
 402   // FP Store Multiple
 403   InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 404                                InstrStage<1, [A8_NLSPipe], 0>,
 405                                InstrStage<1, [A8_LSPipe]>,
 406                                InstrStage<1, [A8_NLSPipe], 0>,
 407                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
 408   //
 409   // FP Store Multiple + update
 410   InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 411                                 InstrStage<1, [A8_NLSPipe], 0>,
 412                                 InstrStage<1, [A8_LSPipe]>,
 413                                 InstrStage<1, [A8_NLSPipe], 0>,
 414                                 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
 415
 416   // NEON
 417   // Issue through integer pipeline, and execute in NEON unit.
 418   //
 419   // VLD1
 420   InstrItinData<IIC_VLD1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 421                                InstrStage<2, [A8_NLSPipe], 0>,
 422                                InstrStage<2, [A8_LSPipe]>],
 423                               [2, 1]>,
 424   // VLD1x2
 425   InstrItinData<IIC_VLD1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 426                                InstrStage<2, [A8_NLSPipe], 0>,
 427                                InstrStage<2, [A8_LSPipe]>],
 428                               [2, 2, 1]>,
 429   //
 430   // VLD1x3
 431   InstrItinData<IIC_VLD1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 432                                InstrStage<3, [A8_NLSPipe], 0>,
 433                                InstrStage<3, [A8_LSPipe]>],
 434                               [2, 2, 3, 1]>,
 435   //
 436   // VLD1x4
 437   InstrItinData<IIC_VLD1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 438                                InstrStage<3, [A8_NLSPipe], 0>,
 439                                InstrStage<3, [A8_LSPipe]>],
 440                               [2, 2, 3, 3, 1]>,
 441   //
 442   // VLD1u
 443   InstrItinData<IIC_VLD1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 444                                InstrStage<2, [A8_NLSPipe], 0>,
 445                                InstrStage<2, [A8_LSPipe]>],
 446                               [2, 2, 1]>,
 447   //
 448   // VLD1x2u
 449   InstrItinData<IIC_VLD1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 450                                InstrStage<2, [A8_NLSPipe], 0>,
 451                                InstrStage<2, [A8_LSPipe]>],
 452                               [2, 2, 2, 1]>,
 453   //
 454   // VLD1x3u
 455   InstrItinData<IIC_VLD1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 456                                InstrStage<3, [A8_NLSPipe], 0>,
 457                                InstrStage<3, [A8_LSPipe]>],
 458                               [2, 2, 3, 2, 1]>,
 459   //
 460   // VLD1x4u
 461   InstrItinData<IIC_VLD1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 462                                InstrStage<3, [A8_NLSPipe], 0>,
 463                                InstrStage<3, [A8_LSPipe]>],
 464                               [2, 2, 3, 3, 2, 1]>,
 465   //
 466   // VLD1ln
 467   InstrItinData<IIC_VLD1ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 468                                InstrStage<3, [A8_NLSPipe], 0>,
 469                                InstrStage<3, [A8_LSPipe]>],
 470                               [3, 1, 1, 1]>,
 471   //
 472   // VLD1lnu
 473   InstrItinData<IIC_VLD1lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 474                                InstrStage<3, [A8_NLSPipe], 0>,
 475                                InstrStage<3, [A8_LSPipe]>],
 476                               [3, 2, 1, 1, 1, 1]>,
 477   //
 478   // VLD1dup
 479   InstrItinData<IIC_VLD1dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 480                                InstrStage<2, [A8_NLSPipe], 0>,
 481                                InstrStage<2, [A8_LSPipe]>],
 482                               [2, 1]>,
 483   //
 484   // VLD1dupu
 485   InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 486                                InstrStage<2, [A8_NLSPipe], 0>,
 487                                InstrStage<2, [A8_LSPipe]>],
 488                               [2, 2, 1, 1]>,
 489   //
 490   // VLD2
 491   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 492                                InstrStage<2, [A8_NLSPipe], 0>,
 493                                InstrStage<2, [A8_LSPipe]>],
 494                               [2, 2, 1]>,
 495   //
 496   // VLD2x2
 497   InstrItinData<IIC_VLD2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 498                                InstrStage<3, [A8_NLSPipe], 0>,
 499                                InstrStage<3, [A8_LSPipe]>],
 500                               [2, 2, 3, 3, 1]>,
 501   //
 502   // VLD2ln
 503   InstrItinData<IIC_VLD2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 504                                InstrStage<3, [A8_NLSPipe], 0>,
 505                                InstrStage<3, [A8_LSPipe]>],
 506                               [3, 3, 1, 1, 1, 1]>,
 507   //
 508   // VLD2u
 509   InstrItinData<IIC_VLD2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 510                                InstrStage<2, [A8_NLSPipe], 0>,
 511                                InstrStage<2, [A8_LSPipe]>],
 512                               [2, 2, 2, 1, 1, 1]>,
 513   //
 514   // VLD2x2u
 515   InstrItinData<IIC_VLD2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 516                                InstrStage<3, [A8_NLSPipe], 0>,
 517                                InstrStage<3, [A8_LSPipe]>],
 518                               [2, 2, 3, 3, 2, 1]>,
 519   //
 520   // VLD2lnu
 521   InstrItinData<IIC_VLD2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 522                                InstrStage<3, [A8_NLSPipe], 0>,
 523                                InstrStage<3, [A8_LSPipe]>],
 524                               [3, 3, 2, 1, 1, 1, 1, 1]>,
 525   //
 526   // VLD2dup
 527   InstrItinData<IIC_VLD2dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 528                                InstrStage<2, [A8_NLSPipe], 0>,
 529                                InstrStage<2, [A8_LSPipe]>],
 530                               [2, 1]>,
 531   //
 532   // VLD2dupu
 533   InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 534                                InstrStage<2, [A8_NLSPipe], 0>,
 535                                InstrStage<2, [A8_LSPipe]>],
 536                               [2, 2, 1, 1]>,
 537   //
 538   // VLD3
 539   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 540                                InstrStage<4, [A8_NLSPipe], 0>,
 541                                InstrStage<4, [A8_LSPipe]>],
 542                               [3, 3, 4, 1]>,
 543   //
 544   // VLD3ln
 545   InstrItinData<IIC_VLD3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 546                                InstrStage<5, [A8_NLSPipe], 0>,
 547                                InstrStage<5, [A8_LSPipe]>],
 548                               [4, 4, 5, 1, 1, 1, 1, 2]>,
 549   //
 550   // VLD3u
 551   InstrItinData<IIC_VLD3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 552                                InstrStage<4, [A8_NLSPipe], 0>,
 553                                InstrStage<4, [A8_LSPipe]>],
 554                               [3, 3, 4, 2, 1]>,
 555   //
 556   // VLD3lnu
 557   InstrItinData<IIC_VLD3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 558                                InstrStage<5, [A8_NLSPipe], 0>,
 559                                InstrStage<5, [A8_LSPipe]>],
 560                               [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
 561   //
 562   // VLD4
 563   InstrItinData<IIC_VLD4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 564                                InstrStage<4, [A8_NLSPipe], 0>,
 565                                InstrStage<4, [A8_LSPipe]>],
 566                               [3, 3, 4, 4, 1]>,
 567   //
 568   // VLD4ln
 569   InstrItinData<IIC_VLD4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 570                                InstrStage<5, [A8_NLSPipe], 0>,
 571                                InstrStage<5, [A8_LSPipe]>],
 572                               [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
 573   //
 574   // VLD4u
 575   InstrItinData<IIC_VLD4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 576                                InstrStage<4, [A8_NLSPipe], 0>,
 577                                InstrStage<4, [A8_LSPipe]>],
 578                               [3, 3, 4, 4, 2, 1]>,
 579   //
 580   // VLD4lnu
 581   InstrItinData<IIC_VLD4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 582                                InstrStage<5, [A8_NLSPipe], 0>,
 583                                InstrStage<5, [A8_LSPipe]>],
 584                               [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
 585   //
 586   // VST1
 587   InstrItinData<IIC_VST1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 588                                InstrStage<2, [A8_NLSPipe], 0>,
 589                                InstrStage<2, [A8_LSPipe]>],
 590                               [1, 1, 1]>,
 591   //
 592   // VST1x2
 593   InstrItinData<IIC_VST1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 594                                InstrStage<2, [A8_NLSPipe], 0>,
 595                                InstrStage<2, [A8_LSPipe]>],
 596                               [1, 1, 1, 1]>,
 597   //
 598   // VST1x3
 599   InstrItinData<IIC_VST1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 600                                InstrStage<3, [A8_NLSPipe], 0>,
 601                                InstrStage<3, [A8_LSPipe]>],
 602                               [1, 1, 1, 1, 2]>,
 603   //
 604   // VST1x4
 605   InstrItinData<IIC_VST1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 606                                InstrStage<3, [A8_NLSPipe], 0>,
 607                                InstrStage<3, [A8_LSPipe]>],
 608                               [1, 1, 1, 1, 2, 2]>,
 609   //
 610   // VST1u
 611   InstrItinData<IIC_VST1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 612                                InstrStage<2, [A8_NLSPipe], 0>,
 613                                InstrStage<2, [A8_LSPipe]>],
 614                               [2, 1, 1, 1, 1]>,
 615   //
 616   // VST1x2u
 617   InstrItinData<IIC_VST1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 618                                InstrStage<2, [A8_NLSPipe], 0>,
 619                                InstrStage<2, [A8_LSPipe]>],
 620                               [2, 1, 1, 1, 1, 1]>,
 621   //
 622   // VST1x3u
 623   InstrItinData<IIC_VST1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 624                                InstrStage<3, [A8_NLSPipe], 0>,
 625                                InstrStage<3, [A8_LSPipe]>],
 626                               [2, 1, 1, 1, 1, 1, 2]>,
 627   //
 628   // VST1x4u
 629   InstrItinData<IIC_VST1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 630                                InstrStage<3, [A8_NLSPipe], 0>,
 631                                InstrStage<3, [A8_LSPipe]>],
 632                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 633   //
 634   // VST1ln
 635   InstrItinData<IIC_VST1ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 636                                InstrStage<2, [A8_NLSPipe], 0>,
 637                                InstrStage<2, [A8_LSPipe]>],
 638                               [1, 1, 1]>,
 639   //
 640   // VST1lnu
 641   InstrItinData<IIC_VST1lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 642                                InstrStage<2, [A8_NLSPipe], 0>,
 643                                InstrStage<2, [A8_LSPipe]>],
 644                               [2, 1, 1, 1, 1]>,
 645   //
 646   // VST2
 647   InstrItinData<IIC_VST2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 648                                InstrStage<2, [A8_NLSPipe], 0>,
 649                                InstrStage<2, [A8_LSPipe]>],
 650                               [1, 1, 1, 1]>,
 651   //
 652   // VST2x2
 653   InstrItinData<IIC_VST2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 654                                InstrStage<4, [A8_NLSPipe], 0>,
 655                                InstrStage<4, [A8_LSPipe]>],
 656                               [1, 1, 1, 1, 2, 2]>,
 657   //
 658   // VST2u
 659   InstrItinData<IIC_VST2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 660                                InstrStage<2, [A8_NLSPipe], 0>,
 661                                InstrStage<2, [A8_LSPipe]>],
 662                               [2, 1, 1, 1, 1, 1]>,
 663   //
 664   // VST2x2u
 665   InstrItinData<IIC_VST2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 666                                InstrStage<4, [A8_NLSPipe], 0>,
 667                                InstrStage<4, [A8_LSPipe]>],
 668                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 669   //
 670   // VST2ln
 671   InstrItinData<IIC_VST2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 672                                InstrStage<2, [A8_NLSPipe], 0>,
 673                                InstrStage<2, [A8_LSPipe]>],
 674                               [1, 1, 1, 1]>,
 675   //
 676   // VST2lnu
 677   InstrItinData<IIC_VST2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 678                                InstrStage<2, [A8_NLSPipe], 0>,
 679                                InstrStage<2, [A8_LSPipe]>],
 680                               [2, 1, 1, 1, 1, 1]>,
 681   //
 682   // VST3
 683   InstrItinData<IIC_VST3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 684                                InstrStage<3, [A8_NLSPipe], 0>,
 685                                InstrStage<3, [A8_LSPipe]>],
 686                               [1, 1, 1, 1, 2]>,
 687   //
 688   // VST3u
 689   InstrItinData<IIC_VST3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 690                                InstrStage<3, [A8_NLSPipe], 0>,
 691                                InstrStage<3, [A8_LSPipe]>],
 692                               [2, 1, 1, 1, 1, 1, 2]>,
 693   //
 694   // VST3ln
 695   InstrItinData<IIC_VST3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 696                                InstrStage<3, [A8_NLSPipe], 0>,
 697                                InstrStage<3, [A8_LSPipe]>],
 698                               [1, 1, 1, 1, 2]>,
 699   //
 700   // VST3lnu
 701   InstrItinData<IIC_VST3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 702                                InstrStage<3, [A8_NLSPipe], 0>,
 703                                InstrStage<3, [A8_LSPipe]>],
 704                               [2, 1, 1, 1, 1, 1, 2]>,
 705   //
 706   // VST4
 707   InstrItinData<IIC_VST4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 708                                InstrStage<4, [A8_NLSPipe], 0>,
 709                                InstrStage<4, [A8_LSPipe]>],
 710                               [1, 1, 1, 1, 2, 2]>,
 711   //
 712   // VST4u
 713   InstrItinData<IIC_VST4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 714                                InstrStage<4, [A8_NLSPipe], 0>,
 715                                InstrStage<4, [A8_LSPipe]>],
 716                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 717   //
 718   // VST4ln
 719   InstrItinData<IIC_VST4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 720                                InstrStage<4, [A8_NLSPipe], 0>,
 721                                InstrStage<4, [A8_LSPipe]>],
 722                               [1, 1, 1, 1, 2, 2]>,
 723   //
 724   // VST4lnu
 725   InstrItinData<IIC_VST4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 726                                InstrStage<4, [A8_NLSPipe], 0>,
 727                                InstrStage<4, [A8_LSPipe]>],
 728                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 729   //
 730   // Double-register FP Unary
 731   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 732                                InstrStage<1, [A8_NPipe]>], [5, 2]>,
 733   //
 734   // Quad-register FP Unary
 735   // Result written in N5, but that is relative to the last cycle of multicycle,
 736   // so we use 6 for those cases
 737   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 738                                InstrStage<2, [A8_NPipe]>], [6, 2]>,
 739   //
 740   // Double-register FP Binary
 741   InstrItinData<IIC_VBIND,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 742                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 743   //
 744   // VPADD, etc.
 745   InstrItinData<IIC_VPBIND,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 746                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 747   //
 748   // Double-register FP VMUL
 749   InstrItinData<IIC_VFMULD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 750                                InstrStage<1, [A8_NPipe]>], [5, 2, 1]>,
 751
 752   //
 753   // Quad-register FP Binary
 754   // Result written in N5, but that is relative to the last cycle of multicycle,
 755   // so we use 6 for those cases
 756   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 757                                InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
 758   //
 759   // Quad-register FP VMUL
 760   InstrItinData<IIC_VFMULQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 761                                InstrStage<1, [A8_NPipe]>], [6, 2, 1]>,
 762   //
 763   // Move
 764   InstrItinData<IIC_VMOV,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 765                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 766   //
 767   // Move Immediate
 768   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 769                                InstrStage<1, [A8_NPipe]>], [3]>,
 770   //
 771   // Double-register Permute Move
 772   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 773                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 774   //
 775   // Quad-register Permute Move
 776   // Result written in N2, but that is relative to the last cycle of multicycle,
 777   // so we use 3 for those cases
 778   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 779                                InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
 780   //
 781   // Integer to Single-precision Move
 782   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 783                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 784   //
 785   // Integer to Double-precision Move
 786   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 787                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 788   //
 789   // Single-precision to Integer Move
 790   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 791                                InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
 792   //
 793   // Double-precision to Integer Move
 794   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 795                                InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
 796   //
 797   // Integer to Lane Move
 798   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 799                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 800   //
 801   // Vector narrow move
 802   InstrItinData<IIC_VMOVN   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 803                                InstrStage<1, [A8_NPipe]>], [2, 1]>,
 804   //
 805   // Double-register Permute
 806   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 807                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
 808   //
 809   // Quad-register Permute
 810   // Result written in N2, but that is relative to the last cycle of multicycle,
 811   // so we use 3 for those cases
 812   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 813                                InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
 814   //
 815   // Quad-register Permute (3 cycle issue)
 816   // Result written in N2, but that is relative to the last cycle of multicycle,
 817   // so we use 4 for those cases
 818   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 819                                InstrStage<1, [A8_NLSPipe]>,
 820                                InstrStage<1, [A8_NPipe], 0>,
 821                                InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
 822   //
 823   // Double-register FP Multiple-Accumulate
 824   InstrItinData<IIC_VMACD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 825                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 826   //
 827   // Quad-register FP Multiple-Accumulate
 828   // Result written in N9, but that is relative to the last cycle of multicycle,
 829   // so we use 10 for those cases
 830   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 831                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 832   //
 833   // Double-register Reciprical Step
 834   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 835                                InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
 836   //
 837   // Quad-register Reciprical Step
 838   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 839                                InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
 840   //
 841   // Double-register Integer Count
 842   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 843                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 844   //
 845   // Quad-register Integer Count
 846   // Result written in N3, but that is relative to the last cycle of multicycle,
 847   // so we use 4 for those cases
 848   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 849                                InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
 850   //
 851   // Double-register Integer Unary
 852   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 853                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 854   //
 855   // Quad-register Integer Unary
 856   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 857                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 858   //
 859   // Double-register Integer Q-Unary
 860   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 861                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 862   //
 863   // Quad-register Integer CountQ-Unary
 864   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 865                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 866   //
 867   // Double-register Integer Binary
 868   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 869                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 870   //
 871   // Quad-register Integer Binary
 872   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 873                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 874   //
 875   // Double-register Integer Binary (4 cycle)
 876   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 877                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 878   //
 879   // Quad-register Integer Binary (4 cycle)
 880   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 881                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 882
 883   //
 884   // Double-register Integer Subtract
 885   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 886                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 887   //
 888   // Quad-register Integer Subtract
 889   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 890                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 891   //
 892   // Double-register Integer Subtract
 893   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 894                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 895   //
 896   // Quad-register Integer Subtract
 897   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 898                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 899   //
 900   // Double-register Integer Shift
 901   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 902                                InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
 903   //
 904   // Quad-register Integer Shift
 905   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 906                                InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
 907   //
 908   // Double-register Integer Shift (4 cycle)
 909   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 910                                InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
 911   //
 912   // Quad-register Integer Shift (4 cycle)
 913   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 914                                InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
 915   //
 916   // Double-register Integer Pair Add Long
 917   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 918                                InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
 919   //
 920   // Quad-register Integer Pair Add Long
 921   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 922                                InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
 923   //
 924   // Double-register Absolute Difference and Accumulate
 925   InstrItinData<IIC_VABAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 926                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
 927   //
 928   // Quad-register Absolute Difference and Accumulate
 929   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 930                                InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
 931
 932   //
 933   // Double-register Integer Multiply (.8, .16)
 934   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 935                                InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
 936   //
 937   // Double-register Integer Multiply (.32)
 938   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 939                                InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
 940   //
 941   // Quad-register Integer Multiply (.8, .16)
 942   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 943                                InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
 944   //
 945   // Quad-register Integer Multiply (.32)
 946   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 947                                InstrStage<1, [A8_NPipe]>,
 948                                InstrStage<2, [A8_NLSPipe], 0>,
 949                                InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
 950   //
 951   // Double-register Integer Multiply-Accumulate (.8, .16)
 952   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 953                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
 954   //
 955   // Double-register Integer Multiply-Accumulate (.32)
 956   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 957                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
 958   //
 959   // Quad-register Integer Multiply-Accumulate (.8, .16)
 960   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 961                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
 962   //
 963   // Quad-register Integer Multiply-Accumulate (.32)
 964   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 965                                InstrStage<1, [A8_NPipe]>,
 966                                InstrStage<2, [A8_NLSPipe], 0>,
 967                                InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
 968   //
 969   // Double-register VEXT
 970   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 971                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 972   //
 973   // Quad-register VEXT
 974   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 975                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 976   //
 977   // VTB
 978   InstrItinData<IIC_VTB1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 979                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
 980   InstrItinData<IIC_VTB2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 981                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
 982   InstrItinData<IIC_VTB3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 983                                InstrStage<1, [A8_NLSPipe]>,
 984                                InstrStage<1, [A8_NPipe], 0>,
 985                                InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
 986   InstrItinData<IIC_VTB4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 987                                InstrStage<1, [A8_NLSPipe]>,
 988                                InstrStage<1, [A8_NPipe], 0>,
 989                                InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
 990   //
 991   // VTBX
 992   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 993                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
 994   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 995                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
 996   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 997                                InstrStage<1, [A8_NLSPipe]>,
 998                                InstrStage<1, [A8_NPipe], 0>,
 999                                InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
1000   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
1001                                InstrStage<1, [A8_NLSPipe]>,
1002                                InstrStage<1, [A8_NPipe], 0>,
1003                             InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
1004 ]>;