1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
12 //===----------------------------------------------------------------------===//
15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
17 def A8_Pipe0 : FuncUnit; // pipeline 0
18 def A8_Pipe1 : FuncUnit; // pipeline 1
19 def A8_LSPipe : FuncUnit; // Load / store pipeline
20 def A8_NPipe : FuncUnit; // NEON ALU/MUL pipe
21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
25 def CortexA8Itineraries : ProcessorItineraries<
26 [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
28 // Two fully-pipelined integer ALU pipelines
31 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
33 // Binary Instructions that produce a result
34 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
35 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
36 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
37 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
40 // Bitwise Instructions that produce a result
41 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
42 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
43 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
44 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
46 // Unary Instructions that produce a result
47 InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
48 InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
50 // Zero and sign extension instructions
51 InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
52 InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
53 InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
55 // Compare instructions
56 InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
57 InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
58 InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
59 InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
62 InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
63 InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
64 InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
65 InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
67 // Move instructions, unconditional
68 InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
69 InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
70 InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
71 InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
72 InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
73 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
75 // Move instructions, conditional
76 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
77 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
78 InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
79 InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
80 InstrItinData<IIC_iCMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
81 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3, 1]>,
84 InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
85 InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
86 InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
87 InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
89 // Integer multiply pipeline
90 // Result written in E5, but that is relative to the last cycle of multicycle,
91 // so we use 6 for those cases
93 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
94 InstrItinData<IIC_iMAC16 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
95 InstrItinData<IIC_iMUL32 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
96 InstrItinData<IIC_iMAC32 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
97 InstrItinData<IIC_iMUL64 , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
98 InstrItinData<IIC_iMAC64 , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
100 // Integer load pipeline
103 InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
104 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
105 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
106 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
107 InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
108 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
111 InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
112 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
113 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
114 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
115 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
116 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
118 // Scaled register offset, issues over 2 cycles
119 // FIXME: lsl by 2 takes 1 cycle.
120 InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
121 InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
122 InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
123 InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
125 // Immediate offset with update
126 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
127 InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
128 InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
129 InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
131 // Register offset with update
132 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
133 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
134 InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
135 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
136 InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
137 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
139 // Scaled register offset with update, issues over 2 cycles
140 InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
141 InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
142 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
143 InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
145 // Load multiple, def is the 5th operand. Pipeline 0 only.
146 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
147 InstrItinData<IIC_iLoad_m , [InstrStage<2, [A8_Pipe0], 0>,
148 InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
150 // Load multiple + update, defs are the 1st and 5th operands.
151 InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>,
152 InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
154 // Load multiple plus branch
155 InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>,
156 InstrStage<3, [A8_LSPipe]>,
157 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
160 // Pop, def is the 3rd operand.
161 InstrItinData<IIC_iPop , [InstrStage<3, [A8_Pipe0], 0>,
162 InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
164 // Push, def is the 3th operand.
165 InstrItinData<IIC_iPop_Br, [InstrStage<3, [A8_Pipe0], 0>,
166 InstrStage<3, [A8_LSPipe]>,
167 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
171 // iLoadi + iALUr for t2LDRpci_pic.
172 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
173 InstrStage<1, [A8_LSPipe]>,
174 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
177 // Integer store pipeline
180 InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
181 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
182 InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
183 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
184 InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
185 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
188 InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
189 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
190 InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
191 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
192 InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
193 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
195 // Scaled register offset, issues over 2 cycles
196 InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
197 InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
198 InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
199 InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
201 // Immediate offset with update
202 InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
203 InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
204 InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
205 InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
207 // Register offset with update
208 InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
209 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
210 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
211 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
212 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
213 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
215 // Scaled register offset with update, issues over 2 cycles
216 InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
217 InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
218 InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
219 InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
221 // Store multiple. Pipeline 0 only.
222 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
223 InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>,
224 InstrStage<2, [A8_LSPipe]>]>,
226 // Store multiple + update
227 InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>,
228 InstrStage<2, [A8_LSPipe]>], [2]>,
232 InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
236 // no delay slots, so the latency of a branch is unimportant
237 InstrItinData<IIC_Br , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
240 // Issue through integer pipeline, and execute in NEON unit. We assume
241 // RunFast mode so that NFP pipeline is used for single-precision when
244 // FP Special Register to Integer Register File Move
245 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
246 InstrStage<1, [A8_NLSPipe]>], [20]>,
248 // Single-precision FP Unary
249 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
250 InstrStage<1, [A8_NPipe]>], [7, 1]>,
252 // Double-precision FP Unary
253 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
254 InstrStage<4, [A8_NPipe], 0>,
255 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
257 // Single-precision FP Compare
258 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
259 InstrStage<1, [A8_NPipe]>], [1, 1]>,
261 // Double-precision FP Compare
262 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
263 InstrStage<4, [A8_NPipe], 0>,
264 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
266 // Single to Double FP Convert
267 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
268 InstrStage<7, [A8_NPipe], 0>,
269 InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
271 // Double to Single FP Convert
272 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
273 InstrStage<5, [A8_NPipe], 0>,
274 InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
276 // Single-Precision FP to Integer Convert
277 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
278 InstrStage<1, [A8_NPipe]>], [7, 1]>,
280 // Double-Precision FP to Integer Convert
281 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
282 InstrStage<8, [A8_NPipe], 0>,
283 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
285 // Integer to Single-Precision FP Convert
286 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
287 InstrStage<1, [A8_NPipe]>], [7, 1]>,
289 // Integer to Double-Precision FP Convert
290 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
291 InstrStage<8, [A8_NPipe], 0>,
292 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
294 // Single-precision FP ALU
295 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
296 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
298 // Double-precision FP ALU
299 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
300 InstrStage<9, [A8_NPipe], 0>,
301 InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
303 // Single-precision FP Multiply
304 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
305 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
307 // Double-precision FP Multiply
308 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
309 InstrStage<11, [A8_NPipe], 0>,
310 InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
312 // Single-precision FP MAC
313 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
314 InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
316 // Double-precision FP MAC
317 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
318 InstrStage<19, [A8_NPipe], 0>,
319 InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
321 // Single-precision FP DIV
322 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
323 InstrStage<20, [A8_NPipe], 0>,
324 InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
326 // Double-precision FP DIV
327 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
328 InstrStage<29, [A8_NPipe], 0>,
329 InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
331 // Single-precision FP SQRT
332 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
333 InstrStage<19, [A8_NPipe], 0>,
334 InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
336 // Double-precision FP SQRT
337 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
338 InstrStage<29, [A8_NPipe], 0>,
339 InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
342 // Integer to Single-precision Move
343 InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
344 InstrStage<1, [A8_NPipe]>],
347 // Integer to Double-precision Move
348 InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
349 InstrStage<1, [A8_NPipe]>],
352 // Single-precision to Integer Move
353 InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
354 InstrStage<1, [A8_NPipe]>],
357 // Double-precision to Integer Move
358 InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
359 InstrStage<1, [A8_NPipe]>],
363 // Single-precision FP Load
364 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
365 InstrStage<1, [A8_NLSPipe], 0>,
366 InstrStage<1, [A8_LSPipe]>],
369 // Double-precision FP Load
370 InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
371 InstrStage<1, [A8_NLSPipe], 0>,
372 InstrStage<1, [A8_LSPipe]>],
376 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
377 InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
378 InstrStage<1, [A8_NLSPipe], 0>,
379 InstrStage<1, [A8_LSPipe]>,
380 InstrStage<1, [A8_NLSPipe], 0>,
381 InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
383 // FP Load Multiple + update
384 InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
385 InstrStage<1, [A8_NLSPipe], 0>,
386 InstrStage<1, [A8_LSPipe]>,
387 InstrStage<1, [A8_NLSPipe], 0>,
388 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
390 // Single-precision FP Store
391 InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
392 InstrStage<1, [A8_NLSPipe], 0>,
393 InstrStage<1, [A8_LSPipe]>],
396 // Double-precision FP Store
397 InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
398 InstrStage<1, [A8_NLSPipe], 0>,
399 InstrStage<1, [A8_LSPipe]>],
403 InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
404 InstrStage<1, [A8_NLSPipe], 0>,
405 InstrStage<1, [A8_LSPipe]>,
406 InstrStage<1, [A8_NLSPipe], 0>,
407 InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
409 // FP Store Multiple + update
410 InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
411 InstrStage<1, [A8_NLSPipe], 0>,
412 InstrStage<1, [A8_LSPipe]>,
413 InstrStage<1, [A8_NLSPipe], 0>,
414 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
417 // Issue through integer pipeline, and execute in NEON unit.
420 InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
421 InstrStage<2, [A8_NLSPipe], 0>,
422 InstrStage<2, [A8_LSPipe]>],
425 InstrItinData<IIC_VLD1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
426 InstrStage<2, [A8_NLSPipe], 0>,
427 InstrStage<2, [A8_LSPipe]>],
431 InstrItinData<IIC_VLD1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
432 InstrStage<3, [A8_NLSPipe], 0>,
433 InstrStage<3, [A8_LSPipe]>],
437 InstrItinData<IIC_VLD1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
438 InstrStage<3, [A8_NLSPipe], 0>,
439 InstrStage<3, [A8_LSPipe]>],
443 InstrItinData<IIC_VLD1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
444 InstrStage<2, [A8_NLSPipe], 0>,
445 InstrStage<2, [A8_LSPipe]>],
449 InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
450 InstrStage<2, [A8_NLSPipe], 0>,
451 InstrStage<2, [A8_LSPipe]>],
455 InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
456 InstrStage<3, [A8_NLSPipe], 0>,
457 InstrStage<3, [A8_LSPipe]>],
461 InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
462 InstrStage<3, [A8_NLSPipe], 0>,
463 InstrStage<3, [A8_LSPipe]>],
467 InstrItinData<IIC_VLD1ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
468 InstrStage<3, [A8_NLSPipe], 1>,
469 InstrStage<3, [A8_LSPipe]>],
473 InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
474 InstrStage<3, [A8_NLSPipe], 1>,
475 InstrStage<3, [A8_LSPipe]>],
479 InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
480 InstrStage<2, [A8_NLSPipe], 0>,
481 InstrStage<2, [A8_LSPipe]>],
485 InstrItinData<IIC_VLD2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
486 InstrStage<3, [A8_NLSPipe], 0>,
487 InstrStage<3, [A8_LSPipe]>],
491 InstrItinData<IIC_VLD2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
492 InstrStage<3, [A8_NLSPipe], 0>,
493 InstrStage<3, [A8_LSPipe]>],
497 InstrItinData<IIC_VLD2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
498 InstrStage<2, [A8_NLSPipe], 0>,
499 InstrStage<2, [A8_LSPipe]>],
503 InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
504 InstrStage<3, [A8_NLSPipe], 0>,
505 InstrStage<3, [A8_LSPipe]>],
509 InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
510 InstrStage<3, [A8_NLSPipe], 0>,
511 InstrStage<3, [A8_LSPipe]>],
512 [3, 3, 2, 1, 1, 1, 1, 1]>,
515 InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
516 InstrStage<4, [A8_NLSPipe], 0>,
517 InstrStage<4, [A8_LSPipe]>],
521 InstrItinData<IIC_VLD3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
522 InstrStage<5, [A8_NLSPipe], 0>,
523 InstrStage<5, [A8_LSPipe]>],
524 [4, 4, 5, 1, 1, 1, 1, 2]>,
527 InstrItinData<IIC_VLD3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
528 InstrStage<4, [A8_NLSPipe], 0>,
529 InstrStage<4, [A8_LSPipe]>],
533 InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
534 InstrStage<5, [A8_NLSPipe], 0>,
535 InstrStage<5, [A8_LSPipe]>],
536 [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
539 InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
540 InstrStage<4, [A8_NLSPipe], 0>,
541 InstrStage<4, [A8_LSPipe]>],
545 InstrItinData<IIC_VLD4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
546 InstrStage<5, [A8_NLSPipe], 0>,
547 InstrStage<5, [A8_LSPipe]>],
548 [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
551 InstrItinData<IIC_VLD4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
552 InstrStage<4, [A8_NLSPipe], 0>,
553 InstrStage<4, [A8_LSPipe]>],
557 InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
558 InstrStage<5, [A8_NLSPipe], 0>,
559 InstrStage<5, [A8_LSPipe]>],
560 [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
563 InstrItinData<IIC_VST1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
564 InstrStage<2, [A8_NLSPipe], 0>,
565 InstrStage<2, [A8_LSPipe]>],
569 InstrItinData<IIC_VST1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
570 InstrStage<2, [A8_NLSPipe], 0>,
571 InstrStage<2, [A8_LSPipe]>],
575 InstrItinData<IIC_VST1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
576 InstrStage<3, [A8_NLSPipe], 0>,
577 InstrStage<3, [A8_LSPipe]>],
581 InstrItinData<IIC_VST1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
582 InstrStage<3, [A8_NLSPipe], 0>,
583 InstrStage<3, [A8_LSPipe]>],
587 InstrItinData<IIC_VST1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
588 InstrStage<2, [A8_NLSPipe], 0>,
589 InstrStage<2, [A8_LSPipe]>],
593 InstrItinData<IIC_VST1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
594 InstrStage<2, [A8_NLSPipe], 0>,
595 InstrStage<2, [A8_LSPipe]>],
599 InstrItinData<IIC_VST1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
600 InstrStage<3, [A8_NLSPipe], 0>,
601 InstrStage<3, [A8_LSPipe]>],
602 [2, 1, 1, 1, 1, 1, 2]>,
605 InstrItinData<IIC_VST1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
606 InstrStage<3, [A8_NLSPipe], 0>,
607 InstrStage<3, [A8_LSPipe]>],
608 [2, 1, 1, 1, 1, 1, 2, 2]>,
611 InstrItinData<IIC_VST1ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
612 InstrStage<2, [A8_NLSPipe], 1>,
613 InstrStage<2, [A8_LSPipe]>],
617 InstrItinData<IIC_VST1lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
618 InstrStage<2, [A8_NLSPipe], 1>,
619 InstrStage<2, [A8_LSPipe]>],
623 InstrItinData<IIC_VST2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
624 InstrStage<2, [A8_NLSPipe], 0>,
625 InstrStage<2, [A8_LSPipe]>],
629 InstrItinData<IIC_VST2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
630 InstrStage<4, [A8_NLSPipe], 0>,
631 InstrStage<4, [A8_LSPipe]>],
635 InstrItinData<IIC_VST2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
636 InstrStage<2, [A8_NLSPipe], 0>,
637 InstrStage<2, [A8_LSPipe]>],
641 InstrItinData<IIC_VST2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
642 InstrStage<4, [A8_NLSPipe], 0>,
643 InstrStage<4, [A8_LSPipe]>],
644 [2, 1, 1, 1, 1, 1, 2, 2]>,
647 InstrItinData<IIC_VST2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
648 InstrStage<2, [A8_NLSPipe], 0>,
649 InstrStage<2, [A8_LSPipe]>],
653 InstrItinData<IIC_VST2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
654 InstrStage<2, [A8_NLSPipe], 0>,
655 InstrStage<2, [A8_LSPipe]>],
659 InstrItinData<IIC_VST3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
660 InstrStage<3, [A8_NLSPipe], 0>,
661 InstrStage<3, [A8_LSPipe]>],
665 InstrItinData<IIC_VST3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
666 InstrStage<3, [A8_NLSPipe], 0>,
667 InstrStage<3, [A8_LSPipe]>],
668 [2, 1, 1, 1, 1, 1, 2]>,
671 InstrItinData<IIC_VST3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
672 InstrStage<3, [A8_NLSPipe], 0>,
673 InstrStage<3, [A8_LSPipe]>],
677 InstrItinData<IIC_VST3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
678 InstrStage<3, [A8_NLSPipe], 0>,
679 InstrStage<3, [A8_LSPipe]>],
680 [2, 1, 1, 1, 1, 1, 2]>,
683 InstrItinData<IIC_VST4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
684 InstrStage<4, [A8_NLSPipe], 0>,
685 InstrStage<4, [A8_LSPipe]>],
689 InstrItinData<IIC_VST4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
690 InstrStage<4, [A8_NLSPipe], 0>,
691 InstrStage<4, [A8_LSPipe]>],
692 [2, 1, 1, 1, 1, 1, 2, 2]>,
695 InstrItinData<IIC_VST4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
696 InstrStage<4, [A8_NLSPipe], 0>,
697 InstrStage<4, [A8_LSPipe]>],
701 InstrItinData<IIC_VST4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
702 InstrStage<4, [A8_NLSPipe], 0>,
703 InstrStage<4, [A8_LSPipe]>],
704 [2, 1, 1, 1, 1, 1, 2, 2]>,
706 // Double-register FP Unary
707 InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
708 InstrStage<1, [A8_NPipe]>], [5, 2]>,
710 // Quad-register FP Unary
711 // Result written in N5, but that is relative to the last cycle of multicycle,
712 // so we use 6 for those cases
713 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
714 InstrStage<2, [A8_NPipe]>], [6, 2]>,
716 // Double-register FP Binary
717 InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
718 InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
721 InstrItinData<IIC_VPBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
722 InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
724 // Double-register FP VMUL
725 InstrItinData<IIC_VFMULD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
726 InstrStage<1, [A8_NPipe]>], [5, 2, 1]>,
729 // Quad-register FP Binary
730 // Result written in N5, but that is relative to the last cycle of multicycle,
731 // so we use 6 for those cases
732 InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
733 InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
735 // Quad-register FP VMUL
736 InstrItinData<IIC_VFMULQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
737 InstrStage<1, [A8_NPipe]>], [6, 2, 1]>,
740 InstrItinData<IIC_VMOV, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
741 InstrStage<1, [A8_NPipe]>], [1, 1]>,
744 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
745 InstrStage<1, [A8_NPipe]>], [3]>,
747 // Double-register Permute Move
748 InstrItinData<IIC_VMOVD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
749 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
751 // Quad-register Permute Move
752 // Result written in N2, but that is relative to the last cycle of multicycle,
753 // so we use 3 for those cases
754 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
755 InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
757 // Integer to Single-precision Move
758 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
759 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
761 // Integer to Double-precision Move
762 InstrItinData<IIC_VMOVID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
763 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
765 // Single-precision to Integer Move
766 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
767 InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
769 // Double-precision to Integer Move
770 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
771 InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
773 // Integer to Lane Move
774 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
775 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
777 // Vector narrow move
778 InstrItinData<IIC_VMOVN , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
779 InstrStage<1, [A8_NPipe]>], [2, 1]>,
781 // Double-register Permute
782 InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
783 InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
785 // Quad-register Permute
786 // Result written in N2, but that is relative to the last cycle of multicycle,
787 // so we use 3 for those cases
788 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
789 InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
791 // Quad-register Permute (3 cycle issue)
792 // Result written in N2, but that is relative to the last cycle of multicycle,
793 // so we use 4 for those cases
794 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
795 InstrStage<1, [A8_NLSPipe]>,
796 InstrStage<1, [A8_NPipe], 0>,
797 InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
799 // Double-register FP Multiple-Accumulate
800 InstrItinData<IIC_VMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
801 InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
803 // Quad-register FP Multiple-Accumulate
804 // Result written in N9, but that is relative to the last cycle of multicycle,
805 // so we use 10 for those cases
806 InstrItinData<IIC_VMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
807 InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
809 // Double-register Reciprical Step
810 InstrItinData<IIC_VRECSD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
811 InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
813 // Quad-register Reciprical Step
814 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
815 InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
817 // Double-register Integer Count
818 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
819 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
821 // Quad-register Integer Count
822 // Result written in N3, but that is relative to the last cycle of multicycle,
823 // so we use 4 for those cases
824 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
825 InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
827 // Double-register Integer Unary
828 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
829 InstrStage<1, [A8_NPipe]>], [4, 2]>,
831 // Quad-register Integer Unary
832 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
833 InstrStage<1, [A8_NPipe]>], [4, 2]>,
835 // Double-register Integer Q-Unary
836 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
837 InstrStage<1, [A8_NPipe]>], [4, 1]>,
839 // Quad-register Integer CountQ-Unary
840 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
841 InstrStage<1, [A8_NPipe]>], [4, 1]>,
843 // Double-register Integer Binary
844 InstrItinData<IIC_VBINiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
845 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
847 // Quad-register Integer Binary
848 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
849 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
851 // Double-register Integer Binary (4 cycle)
852 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
853 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
855 // Quad-register Integer Binary (4 cycle)
856 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
857 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
860 // Double-register Integer Subtract
861 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
862 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
864 // Quad-register Integer Subtract
865 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
866 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
868 // Double-register Integer Subtract
869 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
870 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
872 // Quad-register Integer Subtract
873 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
874 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
876 // Double-register Integer Shift
877 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
878 InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
880 // Quad-register Integer Shift
881 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
882 InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
884 // Double-register Integer Shift (4 cycle)
885 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
886 InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
888 // Quad-register Integer Shift (4 cycle)
889 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
890 InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
892 // Double-register Integer Pair Add Long
893 InstrItinData<IIC_VPALiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
894 InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
896 // Quad-register Integer Pair Add Long
897 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
898 InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
900 // Double-register Absolute Difference and Accumulate
901 InstrItinData<IIC_VABAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
902 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
904 // Quad-register Absolute Difference and Accumulate
905 InstrItinData<IIC_VABAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
906 InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
909 // Double-register Integer Multiply (.8, .16)
910 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
911 InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
913 // Double-register Integer Multiply (.32)
914 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
915 InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
917 // Quad-register Integer Multiply (.8, .16)
918 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
919 InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
921 // Quad-register Integer Multiply (.32)
922 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
923 InstrStage<1, [A8_NPipe]>,
924 InstrStage<2, [A8_NLSPipe], 0>,
925 InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
927 // Double-register Integer Multiply-Accumulate (.8, .16)
928 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
929 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
931 // Double-register Integer Multiply-Accumulate (.32)
932 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
933 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
935 // Quad-register Integer Multiply-Accumulate (.8, .16)
936 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
937 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
939 // Quad-register Integer Multiply-Accumulate (.32)
940 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
941 InstrStage<1, [A8_NPipe]>,
942 InstrStage<2, [A8_NLSPipe], 0>,
943 InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
945 // Double-register VEXT
946 InstrItinData<IIC_VEXTD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
947 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
949 // Quad-register VEXT
950 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
951 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
954 InstrItinData<IIC_VTB1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
955 InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
956 InstrItinData<IIC_VTB2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
957 InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
958 InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
959 InstrStage<1, [A8_NLSPipe]>,
960 InstrStage<1, [A8_NPipe], 0>,
961 InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
962 InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
963 InstrStage<1, [A8_NLSPipe]>,
964 InstrStage<1, [A8_NPipe], 0>,
965 InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
968 InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
969 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
970 InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
971 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
972 InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
973 InstrStage<1, [A8_NLSPipe]>,
974 InstrStage<1, [A8_NPipe], 0>,
975 InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
976 InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
977 InstrStage<1, [A8_NLSPipe]>,
978 InstrStage<1, [A8_NPipe], 0>,
979 InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>