lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 // Functional Units.
  17 def A8_Pipe0   : FuncUnit; // pipeline 0
  18 def A8_Pipe1   : FuncUnit; // pipeline 1
  19 def A8_LSPipe  : FuncUnit; // Load / store pipeline
  20 def A8_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
  22 //
  23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
  24 //
  25 def CortexA8Itineraries : ProcessorItineraries<
  26   [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
  27   [], [
  28   // Two fully-pipelined integer ALU pipelines
  29   //
  30   // No operand cycles
  31   InstrItinData<IIC_iALUx    , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
  32   //
  33   // Binary Instructions that produce a result
  34   InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  35   InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  36   InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  37   InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
  38   InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  39   //
  40   // Bitwise Instructions that produce a result
  41   InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  42   InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  43   InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  44   InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  45   //
  46   // Unary Instructions that produce a result
  47   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  48   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  49   //
  50   // Zero and sign extension instructions
  51   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  52   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  53   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
  54   //
  55   // Compare instructions
  56   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  57   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  58   InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  59   InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  60   //
  61   // Test instructions
  62   InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  63   InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  64   InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  65   InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  66   //
  67   // Move instructions, unconditional
  68   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  69   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  70   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  71   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  72   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  73                              InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  74   //
  75   // Move instructions, conditional
  76   InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  77   InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  78   InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  79   InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  80   //
  81   // MVN instructions
  82   InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  83   InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  84   InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  85   InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  86
  87   // Integer multiply pipeline
  88   // Result written in E5, but that is relative to the last cycle of multicycle,
  89   // so we use 6 for those cases
  90   //
  91   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
  92   InstrItinData<IIC_iMAC16   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  93   InstrItinData<IIC_iMUL32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
  94   InstrItinData<IIC_iMAC32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  95   InstrItinData<IIC_iMUL64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  96   InstrItinData<IIC_iMAC64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  97
  98   // Integer load pipeline
  99   //
 100   // Immediate offset
 101   InstrItinData<IIC_iLoad_i   , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 102                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 103   InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 104                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 105   InstrItinData<IIC_iLoad_d_i,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 106                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 107   //
 108   // Register offset
 109   InstrItinData<IIC_iLoad_r   , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 110                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 111   InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 112                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 113   InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 114                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 115   //
 116   // Scaled register offset, issues over 2 cycles
 117   // FIXME: lsl by 2 takes 1 cycle.
 118   InstrItinData<IIC_iLoad_si  , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
 119                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 120   InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
 121                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 122   //
 123   // Immediate offset with update
 124   InstrItinData<IIC_iLoad_iu  , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 125                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 126   InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 127                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 128   //
 129   // Register offset with update
 130   InstrItinData<IIC_iLoad_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 131                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 132   InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 133                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 134   InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 135                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 136   //
 137   // Scaled register offset with update, issues over 2 cycles
 138   InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
 139                                  InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>,
 140   InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
 141                                   InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>,
 142   //
 143   // Load multiple, def is the 5th operand. Pipeline 0 only.
 144   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 145   InstrItinData<IIC_iLoad_m  , [InstrStage<1, [A8_Pipe0]>,
 146                                 InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
 147   //
 148   // Load multiple + update, defs are the 1st and 5th operands.
 149   InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A8_Pipe0]>,
 150                                 InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
 151   //
 152   // Load multiple plus branch
 153   InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A8_Pipe0]>,
 154                                 InstrStage<3, [A8_LSPipe]>,
 155                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 156                                [1, 2, 1, 1, 3]>,
 157   //
 158   // Pop, def is the 3rd operand.
 159   InstrItinData<IIC_iPop  ,    [InstrStage<1, [A8_Pipe0]>,
 160                                 InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
 161   //
 162   // Push, def is the 3th operand.
 163   InstrItinData<IIC_iPop_Br,   [InstrStage<1, [A8_Pipe0]>,
 164                                 InstrStage<3, [A8_LSPipe]>,
 165                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 166                                [1, 1, 3]>,
 167
 168   //
 169   // iLoadi + iALUr for t2LDRpci_pic.
 170   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 171                                 InstrStage<1, [A8_LSPipe]>,
 172                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
 173
 174
 175   // Integer store pipeline
 176   //
 177   // Immediate offset
 178   InstrItinData<IIC_iStore_i  , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 179                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 180   InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 181                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 182   InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 183                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 184   //
 185   // Register offset
 186   InstrItinData<IIC_iStore_r  , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 187                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 188   InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 189                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 190   InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 191                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 192   //
 193   // Scaled register offset, issues over 2 cycles
 194   InstrItinData<IIC_iStore_si , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 195                                  InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 196   InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 197                                   InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 198   //
 199   // Immediate offset with update
 200   InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 201                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 202   InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 203                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 204   //
 205   // Register offset with update
 206   InstrItinData<IIC_iStore_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 207                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 208   InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 209                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 210   InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 211                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 212   //
 213   // Scaled register offset with update, issues over 2 cycles
 214   InstrItinData<IIC_iStore_siu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 215                                  InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 216   InstrItinData<IIC_iStore_bh_siu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 217                                    InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 218   //
 219   // Store multiple. Pipeline 0 only.
 220   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 221   InstrItinData<IIC_iStore_m , [InstrStage<1, [A8_Pipe0]>,
 222                                 InstrStage<2, [A8_LSPipe]>]>,
 223   //
 224   // Store multiple + update
 225   InstrItinData<IIC_iStore_mu, [InstrStage<1, [A8_Pipe0]>,
 226                                 InstrStage<2, [A8_LSPipe]>], [2]>,
 227
 228   // Branch
 229   //
 230   // no delay slots, so the latency of a branch is unimportant
 231   InstrItinData<IIC_Br      , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 232
 233   // VFP
 234   // Issue through integer pipeline, and execute in NEON unit. We assume
 235   // RunFast mode so that NFP pipeline is used for single-precision when
 236   // possible.
 237   //
 238   // FP Special Register to Integer Register File Move
 239   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 240                               InstrStage<1, [A8_NLSPipe]>]>,
 241   //
 242   // Single-precision FP Unary
 243   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 244                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 245   //
 246   // Double-precision FP Unary
 247   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 248                                InstrStage<4, [A8_NPipe], 0>,
 249                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 250   //
 251   // Single-precision FP Compare
 252   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 253                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 254   //
 255   // Double-precision FP Compare
 256   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 257                                InstrStage<4, [A8_NPipe], 0>,
 258                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 259   //
 260   // Single to Double FP Convert
 261   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 262                                InstrStage<7, [A8_NPipe], 0>,
 263                                InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
 264   //
 265   // Double to Single FP Convert
 266   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 267                                InstrStage<5, [A8_NPipe], 0>,
 268                                InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
 269   //
 270   // Single-Precision FP to Integer Convert
 271   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 272                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 273   //
 274   // Double-Precision FP to Integer Convert
 275   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 276                                InstrStage<8, [A8_NPipe], 0>,
 277                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 278   //
 279   // Integer to Single-Precision FP Convert
 280   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 281                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 282   //
 283   // Integer to Double-Precision FP Convert
 284   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 285                                InstrStage<8, [A8_NPipe], 0>,
 286                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 287   //
 288   // Single-precision FP ALU
 289   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 290                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 291   //
 292   // Double-precision FP ALU
 293   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 294                                InstrStage<9, [A8_NPipe], 0>,
 295                                InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
 296   //
 297   // Single-precision FP Multiply
 298   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 299                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 300   //
 301   // Double-precision FP Multiply
 302   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 303                                InstrStage<11, [A8_NPipe], 0>,
 304                                InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
 305   //
 306   // Single-precision FP MAC
 307   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 308                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 309   //
 310   // Double-precision FP MAC
 311   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 312                                InstrStage<19, [A8_NPipe], 0>,
 313                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 314   //
 315   // Single-precision FP DIV
 316   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 317                                InstrStage<20, [A8_NPipe], 0>,
 318                                InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
 319   //
 320   // Double-precision FP DIV
 321   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 322                                InstrStage<29, [A8_NPipe], 0>,
 323                                InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
 324   //
 325   // Single-precision FP SQRT
 326   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 327                                InstrStage<19, [A8_NPipe], 0>,
 328                                InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
 329   //
 330   // Double-precision FP SQRT
 331   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 332                                InstrStage<29, [A8_NPipe], 0>,
 333                                InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
 334   //
 335   // Single-precision FP Load
 336   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 337                                InstrStage<1, [A8_NLSPipe]>,
 338                                InstrStage<1, [A8_LSPipe]>],
 339                               [2, 1]>,
 340   //
 341   // Double-precision FP Load
 342   InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 343                                InstrStage<1, [A8_NLSPipe]>,
 344                                InstrStage<1, [A8_LSPipe]>],
 345                               [2, 1]>,
 346   //
 347   // FP Load Multiple
 348   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 349   InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 350                                InstrStage<1, [A8_NLSPipe]>,
 351                                InstrStage<1, [A8_LSPipe]>,
 352                                InstrStage<1, [A8_NLSPipe]>,
 353                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
 354   //
 355   // FP Load Multiple + update
 356   InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 357                                InstrStage<1, [A8_NLSPipe]>,
 358                                InstrStage<1, [A8_LSPipe]>,
 359                                InstrStage<1, [A8_NLSPipe]>,
 360                                InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
 361   //
 362   // Single-precision FP Store
 363   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 364                                InstrStage<1, [A8_NLSPipe]>,
 365                                InstrStage<1, [A8_LSPipe]>],
 366                               [1, 1]>,
 367   //
 368   // Double-precision FP Store
 369   InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 370                                InstrStage<1, [A8_NLSPipe]>,
 371                                InstrStage<1, [A8_LSPipe]>],
 372                               [1, 1]>,
 373   //
 374   // FP Store Multiple
 375   InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 376                                InstrStage<1, [A8_NLSPipe]>,
 377                                InstrStage<1, [A8_LSPipe]>,
 378                                InstrStage<1, [A8_NLSPipe]>,
 379                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
 380   //
 381   // FP Store Multiple + update
 382   InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 383                                 InstrStage<1, [A8_NLSPipe]>,
 384                                 InstrStage<1, [A8_LSPipe]>,
 385                                 InstrStage<1, [A8_NLSPipe]>,
 386                                 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
 387
 388   // NEON
 389   // Issue through integer pipeline, and execute in NEON unit.
 390   //
 391   // VLD1
 392   InstrItinData<IIC_VLD1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 393                                InstrStage<2, [A8_NLSPipe], 1>,
 394                                InstrStage<2, [A8_LSPipe]>],
 395                               [2, 1]>,
 396   // VLD1x2
 397   InstrItinData<IIC_VLD1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 398                                InstrStage<2, [A8_NLSPipe], 1>,
 399                                InstrStage<2, [A8_LSPipe]>],
 400                               [2, 2, 1]>,
 401   //
 402   // VLD1x3
 403   InstrItinData<IIC_VLD1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 404                                InstrStage<3, [A8_NLSPipe], 1>,
 405                                InstrStage<3, [A8_LSPipe]>],
 406                               [2, 2, 3, 1]>,
 407   //
 408   // VLD1x4
 409   InstrItinData<IIC_VLD1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 410                                InstrStage<3, [A8_NLSPipe], 1>,
 411                                InstrStage<3, [A8_LSPipe]>],
 412                               [2, 2, 3, 3, 1]>,
 413   //
 414   // VLD1u
 415   InstrItinData<IIC_VLD1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 416                                InstrStage<2, [A8_NLSPipe], 1>,
 417                                InstrStage<2, [A8_LSPipe]>],
 418                               [2, 2, 1]>,
 419   //
 420   // VLD1x2u
 421   InstrItinData<IIC_VLD1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 422                                InstrStage<2, [A8_NLSPipe], 1>,
 423                                InstrStage<2, [A8_LSPipe]>],
 424                               [2, 2, 2, 1]>,
 425   //
 426   // VLD1x3u
 427   InstrItinData<IIC_VLD1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 428                                InstrStage<3, [A8_NLSPipe], 1>,
 429                                InstrStage<3, [A8_LSPipe]>],
 430                               [2, 2, 3, 2, 1]>,
 431   //
 432   // VLD1x4u
 433   InstrItinData<IIC_VLD1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 434                                InstrStage<3, [A8_NLSPipe], 1>,
 435                                InstrStage<3, [A8_LSPipe]>],
 436                               [2, 2, 3, 3, 2, 1]>,
 437   //
 438   // VLD2
 439   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 440                                InstrStage<2, [A8_NLSPipe], 1>,
 441                                InstrStage<2, [A8_LSPipe]>],
 442                               [2, 2, 1]>,
 443   //
 444   // VLD2x2
 445   InstrItinData<IIC_VLD2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 446                                InstrStage<3, [A8_NLSPipe], 1>,
 447                                InstrStage<3, [A8_LSPipe]>],
 448                               [2, 2, 3, 3, 1]>,
 449   //
 450   // VLD2ln
 451   InstrItinData<IIC_VLD2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 452                                InstrStage<3, [A8_NLSPipe], 1>,
 453                                InstrStage<3, [A8_LSPipe]>],
 454                               [3, 3, 1, 1, 1, 1]>,
 455   //
 456   // VLD2u
 457   InstrItinData<IIC_VLD2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 458                                InstrStage<2, [A8_NLSPipe], 1>,
 459                                InstrStage<2, [A8_LSPipe]>],
 460                               [2, 2, 2, 1, 1, 1]>,
 461   //
 462   // VLD2x2u
 463   InstrItinData<IIC_VLD2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 464                                InstrStage<3, [A8_NLSPipe], 1>,
 465                                InstrStage<3, [A8_LSPipe]>],
 466                               [2, 2, 3, 3, 2, 1]>,
 467   //
 468   // VLD2lnu
 469   InstrItinData<IIC_VLD2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 470                                InstrStage<3, [A8_NLSPipe], 1>,
 471                                InstrStage<3, [A8_LSPipe]>],
 472                               [3, 3, 2, 1, 1, 1, 1, 1]>,
 473   //
 474   // VLD3
 475   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 476                                InstrStage<4, [A8_NLSPipe], 1>,
 477                                InstrStage<4, [A8_LSPipe]>],
 478                               [3, 3, 4, 1]>,
 479   //
 480   // VLD3ln
 481   InstrItinData<IIC_VLD3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 482                                InstrStage<5, [A8_NLSPipe], 1>,
 483                                InstrStage<5, [A8_LSPipe]>],
 484                               [4, 4, 5, 1, 1, 1, 1, 2]>,
 485   //
 486   // VLD3u
 487   InstrItinData<IIC_VLD3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 488                                InstrStage<4, [A8_NLSPipe], 1>,
 489                                InstrStage<4, [A8_LSPipe]>],
 490                               [3, 3, 4, 2, 1]>,
 491   //
 492   // VLD3lnu
 493   InstrItinData<IIC_VLD3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 494                                InstrStage<5, [A8_NLSPipe], 1>,
 495                                InstrStage<5, [A8_LSPipe]>],
 496                               [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
 497   //
 498   // VLD4
 499   InstrItinData<IIC_VLD4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 500                                InstrStage<4, [A8_NLSPipe], 1>,
 501                                InstrStage<4, [A8_LSPipe]>],
 502                               [3, 3, 4, 4, 1]>,
 503   //
 504   // VLD4ln
 505   InstrItinData<IIC_VLD4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 506                                InstrStage<5, [A8_NLSPipe], 1>,
 507                                InstrStage<5, [A8_LSPipe]>],
 508                               [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
 509   //
 510   // VLD4u
 511   InstrItinData<IIC_VLD4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 512                                InstrStage<4, [A8_NLSPipe], 1>,
 513                                InstrStage<4, [A8_LSPipe]>],
 514                               [3, 3, 4, 4, 2, 1]>,
 515   //
 516   // VLD4lnu
 517   InstrItinData<IIC_VLD4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 518                                InstrStage<5, [A8_NLSPipe], 1>,
 519                                InstrStage<5, [A8_LSPipe]>],
 520                               [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
 521   //
 522   // VST1
 523   InstrItinData<IIC_VST1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 524                                InstrStage<2, [A8_NLSPipe], 1>,
 525                                InstrStage<2, [A8_LSPipe]>],
 526                               [1, 1, 1]>,
 527   //
 528   // VST1x2
 529   InstrItinData<IIC_VST1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 530                                InstrStage<2, [A8_NLSPipe], 1>,
 531                                InstrStage<2, [A8_LSPipe]>],
 532                               [1, 1, 1, 1]>,
 533   //
 534   // VST1x3
 535   InstrItinData<IIC_VST1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 536                                InstrStage<3, [A8_NLSPipe], 1>,
 537                                InstrStage<3, [A8_LSPipe]>],
 538                               [1, 1, 1, 1, 2]>,
 539   //
 540   // VST1x4
 541   InstrItinData<IIC_VST1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 542                                InstrStage<3, [A8_NLSPipe], 1>,
 543                                InstrStage<3, [A8_LSPipe]>],
 544                               [1, 1, 1, 1, 2, 2]>,
 545   //
 546   // VST1u
 547   InstrItinData<IIC_VST1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 548                                InstrStage<2, [A8_NLSPipe], 1>,
 549                                InstrStage<2, [A8_LSPipe]>],
 550                               [2, 1, 1, 1, 1]>,
 551   //
 552   // VST1x2u
 553   InstrItinData<IIC_VST1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 554                                InstrStage<2, [A8_NLSPipe], 1>,
 555                                InstrStage<2, [A8_LSPipe]>],
 556                               [2, 1, 1, 1, 1, 1]>,
 557   //
 558   // VST1x3u
 559   InstrItinData<IIC_VST1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 560                                InstrStage<3, [A8_NLSPipe], 1>,
 561                                InstrStage<3, [A8_LSPipe]>],
 562                               [2, 1, 1, 1, 1, 1, 2]>,
 563   //
 564   // VST1x4u
 565   InstrItinData<IIC_VST1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 566                                InstrStage<3, [A8_NLSPipe], 1>,
 567                                InstrStage<3, [A8_LSPipe]>],
 568                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 569   //
 570   // VST2
 571   InstrItinData<IIC_VST2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 572                                InstrStage<2, [A8_NLSPipe], 1>,
 573                                InstrStage<2, [A8_LSPipe]>],
 574                               [1, 1, 1, 1]>,
 575   //
 576   // VST2x2
 577   InstrItinData<IIC_VST2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 578                                InstrStage<4, [A8_NLSPipe], 1>,
 579                                InstrStage<4, [A8_LSPipe]>],
 580                               [1, 1, 1, 1, 2, 2]>,
 581   //
 582   // VST2u
 583   InstrItinData<IIC_VST2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 584                                InstrStage<2, [A8_NLSPipe], 1>,
 585                                InstrStage<2, [A8_LSPipe]>],
 586                               [2, 1, 1, 1, 1, 1]>,
 587   //
 588   // VST2x2u
 589   InstrItinData<IIC_VST2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 590                                InstrStage<4, [A8_NLSPipe], 1>,
 591                                InstrStage<4, [A8_LSPipe]>],
 592                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 593   //
 594   // VST2ln
 595   InstrItinData<IIC_VST2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 596                                InstrStage<2, [A8_NLSPipe], 1>,
 597                                InstrStage<2, [A8_LSPipe]>],
 598                               [1, 1, 1, 1]>,
 599   //
 600   // VST2lnu
 601   InstrItinData<IIC_VST2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 602                                InstrStage<2, [A8_NLSPipe], 1>,
 603                                InstrStage<2, [A8_LSPipe]>],
 604                               [2, 1, 1, 1, 1, 1]>,
 605   //
 606   // VST3
 607   InstrItinData<IIC_VST3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 608                                InstrStage<3, [A8_NLSPipe], 1>,
 609                                InstrStage<3, [A8_LSPipe]>],
 610                               [1, 1, 1, 1, 2]>,
 611   //
 612   // VST3u
 613   InstrItinData<IIC_VST3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 614                                InstrStage<3, [A8_NLSPipe], 1>,
 615                                InstrStage<3, [A8_LSPipe]>],
 616                               [2, 1, 1, 1, 1, 1, 2]>,
 617   //
 618   // VST3ln
 619   InstrItinData<IIC_VST3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 620                                InstrStage<3, [A8_NLSPipe], 1>,
 621                                InstrStage<3, [A8_LSPipe]>],
 622                               [1, 1, 1, 1, 2]>,
 623   //
 624   // VST3lnu
 625   InstrItinData<IIC_VST3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 626                                InstrStage<3, [A8_NLSPipe], 1>,
 627                                InstrStage<3, [A8_LSPipe]>],
 628                               [2, 1, 1, 1, 1, 1, 2]>,
 629   //
 630   // VST4
 631   InstrItinData<IIC_VST4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 632                                InstrStage<4, [A8_NLSPipe], 1>,
 633                                InstrStage<4, [A8_LSPipe]>],
 634                               [1, 1, 1, 1, 2, 2]>,
 635   //
 636   // VST4u
 637   InstrItinData<IIC_VST4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 638                                InstrStage<4, [A8_NLSPipe], 1>,
 639                                InstrStage<4, [A8_LSPipe]>],
 640                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 641   //
 642   // VST4ln
 643   InstrItinData<IIC_VST4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 644                                InstrStage<4, [A8_NLSPipe], 1>,
 645                                InstrStage<4, [A8_LSPipe]>],
 646                               [1, 1, 1, 1, 2, 2]>,
 647   //
 648   // VST4lnu
 649   InstrItinData<IIC_VST4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 650                                InstrStage<4, [A8_NLSPipe], 1>,
 651                                InstrStage<4, [A8_LSPipe]>],
 652                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 653   //
 654   // Double-register FP Unary
 655   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 656                                InstrStage<1, [A8_NPipe]>], [5, 2]>,
 657   //
 658   // Quad-register FP Unary
 659   // Result written in N5, but that is relative to the last cycle of multicycle,
 660   // so we use 6 for those cases
 661   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 662                                InstrStage<2, [A8_NPipe]>], [6, 2]>,
 663   //
 664   // Double-register FP Binary
 665   InstrItinData<IIC_VBIND,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 666                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 667   //
 668   // Quad-register FP Binary
 669   // Result written in N5, but that is relative to the last cycle of multicycle,
 670   // so we use 6 for those cases
 671   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 672                                InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
 673   //
 674   // Move
 675   InstrItinData<IIC_VMOV,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 676                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 677   //
 678   // Move Immediate
 679   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 680                                InstrStage<1, [A8_NPipe]>], [3]>,
 681   //
 682   // Double-register Permute Move
 683   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 684                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 685   //
 686   // Quad-register Permute Move
 687   // Result written in N2, but that is relative to the last cycle of multicycle,
 688   // so we use 3 for those cases
 689   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 690                                InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
 691   //
 692   // Integer to Single-precision Move
 693   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 694                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 695   //
 696   // Integer to Double-precision Move
 697   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 698                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 699   //
 700   // Single-precision to Integer Move
 701   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 702                                InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
 703   //
 704   // Double-precision to Integer Move
 705   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 706                                InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
 707   //
 708   // Integer to Lane Move
 709   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 710                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 711   //
 712   // Vector narrow move
 713   InstrItinData<IIC_VMOVN   , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 714                                InstrStage<1, [A8_NPipe]>], [2, 1]>,
 715   //
 716   // Double-register Permute
 717   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 718                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
 719   //
 720   // Quad-register Permute
 721   // Result written in N2, but that is relative to the last cycle of multicycle,
 722   // so we use 3 for those cases
 723   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 724                                InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
 725   //
 726   // Quad-register Permute (3 cycle issue)
 727   // Result written in N2, but that is relative to the last cycle of multicycle,
 728   // so we use 4 for those cases
 729   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 730                                InstrStage<1, [A8_NLSPipe]>,
 731                                InstrStage<1, [A8_NPipe], 0>,
 732                                InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
 733   //
 734   // Double-register FP Multiple-Accumulate
 735   InstrItinData<IIC_VMACD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 736                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 737   //
 738   // Quad-register FP Multiple-Accumulate
 739   // Result written in N9, but that is relative to the last cycle of multicycle,
 740   // so we use 10 for those cases
 741   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 742                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 743   //
 744   // Double-register Reciprical Step
 745   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 746                                InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
 747   //
 748   // Quad-register Reciprical Step
 749   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 750                                InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
 751   //
 752   // Double-register Integer Count
 753   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 754                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 755   //
 756   // Quad-register Integer Count
 757   // Result written in N3, but that is relative to the last cycle of multicycle,
 758   // so we use 4 for those cases
 759   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 760                                InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
 761   //
 762   // Double-register Integer Unary
 763   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 764                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 765   //
 766   // Quad-register Integer Unary
 767   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 768                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 769   //
 770   // Double-register Integer Q-Unary
 771   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 772                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 773   //
 774   // Quad-register Integer CountQ-Unary
 775   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 776                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 777   //
 778   // Double-register Integer Binary
 779   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 780                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 781   //
 782   // Quad-register Integer Binary
 783   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 784                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 785   //
 786   // Double-register Integer Binary (4 cycle)
 787   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 788                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 789   //
 790   // Quad-register Integer Binary (4 cycle)
 791   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 792                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 793
 794   //
 795   // Double-register Integer Subtract
 796   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 797                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 798   //
 799   // Quad-register Integer Subtract
 800   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 801                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 802   //
 803   // Double-register Integer Subtract
 804   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 805                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 806   //
 807   // Quad-register Integer Subtract
 808   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 809                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 810   //
 811   // Double-register Integer Shift
 812   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 813                                InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
 814   //
 815   // Quad-register Integer Shift
 816   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 817                                InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
 818   //
 819   // Double-register Integer Shift (4 cycle)
 820   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 821                                InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
 822   //
 823   // Quad-register Integer Shift (4 cycle)
 824   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 825                                InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
 826   //
 827   // Double-register Integer Pair Add Long
 828   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 829                                InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
 830   //
 831   // Quad-register Integer Pair Add Long
 832   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 833                                InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
 834   //
 835   // Double-register Absolute Difference and Accumulate
 836   InstrItinData<IIC_VABAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 837                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
 838   //
 839   // Quad-register Absolute Difference and Accumulate
 840   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 841                                InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
 842
 843   //
 844   // Double-register Integer Multiply (.8, .16)
 845   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 846                                InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
 847   //
 848   // Double-register Integer Multiply (.32)
 849   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 850                                InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
 851   //
 852   // Quad-register Integer Multiply (.8, .16)
 853   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 854                                InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
 855   //
 856   // Quad-register Integer Multiply (.32)
 857   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 858                                InstrStage<1, [A8_NPipe]>,
 859                                InstrStage<2, [A8_NLSPipe], 0>,
 860                                InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
 861   //
 862   // Double-register Integer Multiply-Accumulate (.8, .16)
 863   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 864                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
 865   //
 866   // Double-register Integer Multiply-Accumulate (.32)
 867   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 868                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
 869   //
 870   // Quad-register Integer Multiply-Accumulate (.8, .16)
 871   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 872                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
 873   //
 874   // Quad-register Integer Multiply-Accumulate (.32)
 875   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 876                                InstrStage<1, [A8_NPipe]>,
 877                                InstrStage<2, [A8_NLSPipe], 0>,
 878                                InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
 879   //
 880   // Double-register VEXT
 881   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 882                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 883   //
 884   // Quad-register VEXT
 885   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 886                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 887   //
 888   // VTB
 889   InstrItinData<IIC_VTB1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 890                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
 891   InstrItinData<IIC_VTB2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 892                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
 893   InstrItinData<IIC_VTB3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 894                                InstrStage<1, [A8_NLSPipe]>,
 895                                InstrStage<1, [A8_NPipe], 0>,
 896                                InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
 897   InstrItinData<IIC_VTB4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 898                                InstrStage<1, [A8_NLSPipe]>,
 899                                InstrStage<1, [A8_NPipe], 0>,
 900                                InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
 901   //
 902   // VTBX
 903   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 904                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
 905   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 906                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
 907   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 908                                InstrStage<1, [A8_NLSPipe]>,
 909                                InstrStage<1, [A8_NPipe], 0>,
 910                                InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
 911   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 912                                InstrStage<1, [A8_NLSPipe]>,
 913                                InstrStage<1, [A8_NPipe], 0>,
 914                             InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 915 ]>;