lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 // Functional Units.
  17 def A8_Issue   : FuncUnit; // issue
  18 def A8_Pipe0   : FuncUnit; // pipeline 0
  19 def A8_Pipe1   : FuncUnit; // pipeline 1
  20 def A8_LdSt0   : FuncUnit; // pipeline 0 load/store
  21 def A8_LdSt1   : FuncUnit; // pipeline 1 load/store
  22 def A8_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  23 def A8_NLSPipe : FuncUnit; // NEON LS pipe
  24 //
  25 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
  26 //
  27 def CortexA8Itineraries : ProcessorItineraries<
  28   [A8_Issue, A8_Pipe0, A8_Pipe1, A8_LdSt0, A8_LdSt1, A8_NPipe, A8_NLSPipe],
  29   [], [
  30   // Two fully-pipelined integer ALU pipelines
  31   //
  32   // No operand cycles
  33   InstrItinData<IIC_iALUx    , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
  34   //
  35   // Binary Instructions that produce a result
  36   InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  37   InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  38   InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  39   InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  40   //
  41   // Bitwise Instructions that produce a result
  42   InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  43   InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  44   InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  45   InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  46   //
  47   // Unary Instructions that produce a result
  48   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  49   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  50   //
  51   // Zero and sign extension instructions
  52   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  53   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  54   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
  55   //
  56   // Compare instructions
  57   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  58   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  59   InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  60   InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  61   //
  62   // Test instructions
  63   InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  64   InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  65   InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  66   InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  67   //
  68   // Move instructions, unconditional
  69   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  70   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  71   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  72   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  73   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  74                              InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  75   //
  76   // Move instructions, conditional
  77   InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  78   InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  79   InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  80   InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  81   //
  82   // MVN instructions
  83   InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  84   InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  85   InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  86   InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  87
  88   // Integer multiply pipeline
  89   // Result written in E5, but that is relative to the last cycle of multicycle,
  90   // so we use 6 for those cases
  91   //
  92   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
  93   InstrItinData<IIC_iMAC16   , [InstrStage<1, [A8_Pipe1], 0>,
  94                                 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  95   InstrItinData<IIC_iMUL32   , [InstrStage<1, [A8_Pipe1], 0>,
  96                                 InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
  97   InstrItinData<IIC_iMAC32   , [InstrStage<1, [A8_Pipe1], 0>,
  98                                 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  99   InstrItinData<IIC_iMUL64   , [InstrStage<2, [A8_Pipe1], 0>,
 100                                 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
 101   InstrItinData<IIC_iMAC64   , [InstrStage<2, [A8_Pipe1], 0>,
 102                                 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
 103
 104   // Integer load pipeline
 105   //
 106   // loads have an extra cycle of latency, but are fully pipelined
 107   // use A8_Issue to enforce the 1 load/store per cycle limit
 108   //
 109   // Immediate offset
 110   InstrItinData<IIC_iLoadi   , [InstrStage<1, [A8_Issue], 0>,
 111                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 112                                 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
 113   //
 114   // Register offset
 115   InstrItinData<IIC_iLoadr   , [InstrStage<1, [A8_Issue], 0>,
 116                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 117                                 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 118   //
 119   // Scaled register offset, issues over 2 cycles
 120   InstrItinData<IIC_iLoadsi  , [InstrStage<2, [A8_Issue], 0>,
 121                                 InstrStage<1, [A8_Pipe0], 0>,
 122                                 InstrStage<1, [A8_Pipe1]>,
 123                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 124                                 InstrStage<1, [A8_LdSt0]>], [4, 1, 1]>,
 125   //
 126   // Immediate offset with update
 127   InstrItinData<IIC_iLoadiu  , [InstrStage<1, [A8_Issue], 0>,
 128                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 129                                 InstrStage<1, [A8_LdSt0]>], [3, 2, 1]>,
 130   //
 131   // Register offset with update
 132   InstrItinData<IIC_iLoadru  , [InstrStage<1, [A8_Issue], 0>,
 133                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 134                                 InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
 135   //
 136   // Scaled register offset with update, issues over 2 cycles
 137   InstrItinData<IIC_iLoadsiu , [InstrStage<2, [A8_Issue], 0>,
 138                                 InstrStage<1, [A8_Pipe0], 0>,
 139                                 InstrStage<1, [A8_Pipe1]>,
 140                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 141                                 InstrStage<1, [A8_LdSt0]>], [4, 3, 1, 1]>,
 142   //
 143   // Load multiple
 144   InstrItinData<IIC_iLoadm   , [InstrStage<2, [A8_Issue], 0>,
 145                                 InstrStage<2, [A8_Pipe0], 0>,
 146                                 InstrStage<2, [A8_Pipe1]>,
 147                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 148                                 InstrStage<1, [A8_LdSt0]>]>,
 149
 150   //
 151   // Load multiple plus branch
 152   InstrItinData<IIC_iLoadmBr , [InstrStage<2, [A8_Issue], 0>,
 153                                 InstrStage<2, [A8_Pipe0], 0>,
 154                                 InstrStage<2, [A8_Pipe1]>,
 155                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 156                                 InstrStage<1, [A8_LdSt0]>,
 157                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 158
 159   //
 160   // iLoadi + iALUr for t2LDRpci_pic.
 161   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Issue], 0>,
 162                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 163                                 InstrStage<1, [A8_LdSt0]>,
 164                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
 165
 166
 167   // Integer store pipeline
 168   //
 169   // use A8_Issue to enforce the 1 load/store per cycle limit
 170   //
 171   // Immediate offset
 172   InstrItinData<IIC_iStorei  , [InstrStage<1, [A8_Issue], 0>,
 173                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 174                                 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
 175   //
 176   // Register offset
 177   InstrItinData<IIC_iStorer  , [InstrStage<1, [A8_Issue], 0>,
 178                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 179                                 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 180   //
 181   // Scaled register offset, issues over 2 cycles
 182   InstrItinData<IIC_iStoresi , [InstrStage<2, [A8_Issue], 0>,
 183                                 InstrStage<1, [A8_Pipe0], 0>,
 184                                 InstrStage<1, [A8_Pipe1]>,
 185                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 186                                 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
 187   //
 188   // Immediate offset with update
 189   InstrItinData<IIC_iStoreiu , [InstrStage<1, [A8_Issue], 0>,
 190                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 191                                 InstrStage<1, [A8_LdSt0]>], [2, 3, 1]>,
 192   //
 193   // Register offset with update
 194   InstrItinData<IIC_iStoreru  , [InstrStage<1, [A8_Issue], 0>,
 195                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 196                                 InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
 197   //
 198   // Scaled register offset with update, issues over 2 cycles
 199   InstrItinData<IIC_iStoresiu, [InstrStage<2, [A8_Issue], 0>,
 200                                 InstrStage<1, [A8_Pipe0], 0>,
 201                                 InstrStage<1, [A8_Pipe1]>,
 202                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 203                                 InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>,
 204   //
 205   // Store multiple
 206   InstrItinData<IIC_iStorem  , [InstrStage<2, [A8_Issue], 0>,
 207                                 InstrStage<2, [A8_Pipe0], 0>,
 208                                 InstrStage<2, [A8_Pipe1]>,
 209                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 210                                 InstrStage<1, [A8_LdSt0]>]>,
 211
 212   // Branch
 213   //
 214   // no delay slots, so the latency of a branch is unimportant
 215   InstrItinData<IIC_Br      , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 216
 217   // VFP
 218   // Issue through integer pipeline, and execute in NEON unit. We assume
 219   // RunFast mode so that NFP pipeline is used for single-precision when
 220   // possible.
 221   //
 222   // FP Special Register to Integer Register File Move
 223   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 224                               InstrStage<1, [A8_NLSPipe]>]>,
 225   //
 226   // Single-precision FP Unary
 227   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 228                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 229   //
 230   // Double-precision FP Unary
 231   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 232                                InstrStage<4, [A8_NPipe], 0>,
 233                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 234   //
 235   // Single-precision FP Compare
 236   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 237                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 238   //
 239   // Double-precision FP Compare
 240   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 241                                InstrStage<4, [A8_NPipe], 0>,
 242                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 243   //
 244   // Single to Double FP Convert
 245   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 246                                InstrStage<7, [A8_NPipe], 0>,
 247                                InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
 248   //
 249   // Double to Single FP Convert
 250   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 251                                InstrStage<5, [A8_NPipe], 0>,
 252                                InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
 253   //
 254   // Single-Precision FP to Integer Convert
 255   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 256                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 257   //
 258   // Double-Precision FP to Integer Convert
 259   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 260                                InstrStage<8, [A8_NPipe], 0>,
 261                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 262   //
 263   // Integer to Single-Precision FP Convert
 264   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 265                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 266   //
 267   // Integer to Double-Precision FP Convert
 268   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 269                                InstrStage<8, [A8_NPipe], 0>,
 270                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 271   //
 272   // Single-precision FP ALU
 273   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 274                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 275   //
 276   // Double-precision FP ALU
 277   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 278                                InstrStage<9, [A8_NPipe], 0>,
 279                                InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
 280   //
 281   // Single-precision FP Multiply
 282   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 283                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 284   //
 285   // Double-precision FP Multiply
 286   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 287                                InstrStage<11, [A8_NPipe], 0>,
 288                                InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
 289   //
 290   // Single-precision FP MAC
 291   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 292                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 293   //
 294   // Double-precision FP MAC
 295   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 296                                InstrStage<19, [A8_NPipe], 0>,
 297                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 298   //
 299   // Single-precision FP DIV
 300   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 301                                InstrStage<20, [A8_NPipe], 0>,
 302                                InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
 303   //
 304   // Double-precision FP DIV
 305   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 306                                InstrStage<29, [A8_NPipe], 0>,
 307                                InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
 308   //
 309   // Single-precision FP SQRT
 310   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 311                                InstrStage<19, [A8_NPipe], 0>,
 312                                InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
 313   //
 314   // Double-precision FP SQRT
 315   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 316                                InstrStage<29, [A8_NPipe], 0>,
 317                                InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
 318   //
 319   // Single-precision FP Load
 320   // use A8_Issue to enforce the 1 load/store per cycle limit
 321   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>,
 322                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 323                                InstrStage<1, [A8_LdSt0], 0>,
 324                                InstrStage<1, [A8_NLSPipe]>]>,
 325   //
 326   // Double-precision FP Load
 327   // use A8_Issue to enforce the 1 load/store per cycle limit
 328   InstrItinData<IIC_fpLoad64, [InstrStage<2, [A8_Issue], 0>,
 329                                InstrStage<1, [A8_Pipe0], 0>,
 330                                InstrStage<1, [A8_Pipe1]>,
 331                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 332                                InstrStage<1, [A8_LdSt0], 0>,
 333                                InstrStage<1, [A8_NLSPipe]>]>,
 334   //
 335   // FP Load Multiple
 336   // use A8_Issue to enforce the 1 load/store per cycle limit
 337   InstrItinData<IIC_fpLoadm,  [InstrStage<3, [A8_Issue], 0>,
 338                                InstrStage<2, [A8_Pipe0], 0>,
 339                                InstrStage<2, [A8_Pipe1]>,
 340                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 341                                InstrStage<1, [A8_LdSt0], 0>,
 342                                InstrStage<1, [A8_NLSPipe]>]>,
 343   //
 344   // Single-precision FP Store
 345   // use A8_Issue to enforce the 1 load/store per cycle limit
 346   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>,
 347                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 348                                InstrStage<1, [A8_LdSt0], 0>,
 349                                InstrStage<1, [A8_NLSPipe]>]>,
 350   //
 351   // Double-precision FP Store
 352   // use A8_Issue to enforce the 1 load/store per cycle limit
 353   InstrItinData<IIC_fpStore64,[InstrStage<2, [A8_Issue], 0>,
 354                                InstrStage<1, [A8_Pipe0], 0>,
 355                                InstrStage<1, [A8_Pipe1]>,
 356                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 357                                InstrStage<1, [A8_LdSt0], 0>,
 358                                InstrStage<1, [A8_NLSPipe]>]>,
 359   //
 360   // FP Store Multiple
 361   // use A8_Issue to enforce the 1 load/store per cycle limit
 362   InstrItinData<IIC_fpStorem, [InstrStage<3, [A8_Issue], 0>,
 363                                InstrStage<2, [A8_Pipe0], 0>,
 364                                InstrStage<2, [A8_Pipe1]>,
 365                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 366                                InstrStage<1, [A8_LdSt0], 0>,
 367                                InstrStage<1, [A8_NLSPipe]>]>,
 368
 369   // NEON
 370   // Issue through integer pipeline, and execute in NEON unit.
 371   //
 372   // VLD1
 373   // FIXME: We don't model this instruction properly
 374   InstrItinData<IIC_VLD1,     [InstrStage<1, [A8_Issue], 0>,
 375                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 376                                InstrStage<1, [A8_LdSt0], 0>,
 377                                InstrStage<1, [A8_NLSPipe]>]>,
 378   //
 379   // VLD2
 380   // FIXME: We don't model this instruction properly
 381   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Issue], 0>,
 382                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 383                                InstrStage<1, [A8_LdSt0], 0>,
 384                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1]>,
 385   //
 386   // VLD3
 387   // FIXME: We don't model this instruction properly
 388   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Issue], 0>,
 389                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 390                                InstrStage<1, [A8_LdSt0], 0>,
 391                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 1]>,
 392   //
 393   // VLD4
 394   // FIXME: We don't model this instruction properly
 395   InstrItinData<IIC_VLD4,     [InstrStage<1, [A8_Issue], 0>,
 396                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 397                                InstrStage<1, [A8_LdSt0], 0>,
 398                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 2, 1]>,
 399   //
 400   // VST
 401   // FIXME: We don't model this instruction properly
 402   InstrItinData<IIC_VST,      [InstrStage<1, [A8_Issue], 0>,
 403                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 404                                InstrStage<1, [A8_LdSt0], 0>,
 405                                InstrStage<1, [A8_NLSPipe]>]>,
 406   //
 407   // Double-register FP Unary
 408   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 409                                InstrStage<1, [A8_NPipe]>], [5, 2]>,
 410   //
 411   // Quad-register FP Unary
 412   // Result written in N5, but that is relative to the last cycle of multicycle,
 413   // so we use 6 for those cases
 414   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 415                                InstrStage<2, [A8_NPipe]>], [6, 2]>,
 416   //
 417   // Double-register FP Binary
 418   InstrItinData<IIC_VBIND,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 419                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 420   //
 421   // Quad-register FP Binary
 422   // Result written in N5, but that is relative to the last cycle of multicycle,
 423   // so we use 6 for those cases
 424   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 425                                InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
 426   //
 427   // Move Immediate
 428   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 429                                InstrStage<1, [A8_NPipe]>], [3]>,
 430   //
 431   // Double-register Permute Move
 432   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 433                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 434   //
 435   // Quad-register Permute Move
 436   // Result written in N2, but that is relative to the last cycle of multicycle,
 437   // so we use 3 for those cases
 438   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 439                                InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
 440   //
 441   // Integer to Single-precision Move
 442   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 443                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 444   //
 445   // Integer to Double-precision Move
 446   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 447                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 448   //
 449   // Single-precision to Integer Move
 450   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 451                                InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
 452   //
 453   // Double-precision to Integer Move
 454   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 455                                InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
 456   //
 457   // Integer to Lane Move
 458   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 459                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 460   //
 461   // Double-register Permute
 462   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 463                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
 464   //
 465   // Quad-register Permute
 466   // Result written in N2, but that is relative to the last cycle of multicycle,
 467   // so we use 3 for those cases
 468   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 469                                InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
 470   //
 471   // Quad-register Permute (3 cycle issue)
 472   // Result written in N2, but that is relative to the last cycle of multicycle,
 473   // so we use 4 for those cases
 474   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 475                                InstrStage<1, [A8_NLSPipe]>,
 476                                InstrStage<1, [A8_NPipe], 0>,
 477                                InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
 478   //
 479   // Double-register FP Multiple-Accumulate
 480   InstrItinData<IIC_VMACD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 481                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 482   //
 483   // Quad-register FP Multiple-Accumulate
 484   // Result written in N9, but that is relative to the last cycle of multicycle,
 485   // so we use 10 for those cases
 486   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 487                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 488   //
 489   // Double-register Reciprical Step
 490   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 491                                InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
 492   //
 493   // Quad-register Reciprical Step
 494   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 495                                InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
 496   //
 497   // Double-register Integer Count
 498   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 499                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 500   //
 501   // Quad-register Integer Count
 502   // Result written in N3, but that is relative to the last cycle of multicycle,
 503   // so we use 4 for those cases
 504   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 505                                InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
 506   //
 507   // Double-register Integer Unary
 508   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 509                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 510   //
 511   // Quad-register Integer Unary
 512   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 513                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 514   //
 515   // Double-register Integer Q-Unary
 516   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 517                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 518   //
 519   // Quad-register Integer CountQ-Unary
 520   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 521                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 522   //
 523   // Double-register Integer Binary
 524   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 525                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 526   //
 527   // Quad-register Integer Binary
 528   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 529                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 530   //
 531   // Double-register Integer Binary (4 cycle)
 532   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 533                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 534   //
 535   // Quad-register Integer Binary (4 cycle)
 536   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 537                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 538
 539   //
 540   // Double-register Integer Subtract
 541   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 542                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 543   //
 544   // Quad-register Integer Subtract
 545   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 546                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 547   //
 548   // Double-register Integer Subtract
 549   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 550                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 551   //
 552   // Quad-register Integer Subtract
 553   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 554                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 555   //
 556   // Double-register Integer Shift
 557   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 558                                InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
 559   //
 560   // Quad-register Integer Shift
 561   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 562                                InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
 563   //
 564   // Double-register Integer Shift (4 cycle)
 565   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 566                                InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
 567   //
 568   // Quad-register Integer Shift (4 cycle)
 569   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 570                                InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
 571   //
 572   // Double-register Integer Pair Add Long
 573   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 574                                InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
 575   //
 576   // Quad-register Integer Pair Add Long
 577   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 578                                InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
 579   //
 580   // Double-register Absolute Difference and Accumulate
 581   InstrItinData<IIC_VABAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 582                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
 583   //
 584   // Quad-register Absolute Difference and Accumulate
 585   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 586                                InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
 587
 588   //
 589   // Double-register Integer Multiply (.8, .16)
 590   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 591                                InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
 592   //
 593   // Double-register Integer Multiply (.32)
 594   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 595                                InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
 596   //
 597   // Quad-register Integer Multiply (.8, .16)
 598   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 599                                InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
 600   //
 601   // Quad-register Integer Multiply (.32)
 602   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 603                                InstrStage<1, [A8_NPipe]>,
 604                                InstrStage<2, [A8_NLSPipe], 0>,
 605                                InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
 606   //
 607   // Double-register Integer Multiply-Accumulate (.8, .16)
 608   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 609                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
 610   //
 611   // Double-register Integer Multiply-Accumulate (.32)
 612   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 613                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
 614   //
 615   // Quad-register Integer Multiply-Accumulate (.8, .16)
 616   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 617                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
 618   //
 619   // Quad-register Integer Multiply-Accumulate (.32)
 620   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 621                                InstrStage<1, [A8_NPipe]>,
 622                                InstrStage<2, [A8_NLSPipe], 0>,
 623                                InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
 624   //
 625   // Double-register VEXT
 626   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 627                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 628   //
 629   // Quad-register VEXT
 630   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 631                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 632   //
 633   // VTB
 634   InstrItinData<IIC_VTB1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 635                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
 636   InstrItinData<IIC_VTB2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 637                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
 638   InstrItinData<IIC_VTB3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 639                                InstrStage<1, [A8_NLSPipe]>,
 640                                InstrStage<1, [A8_NPipe], 0>,
 641                                InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
 642   InstrItinData<IIC_VTB4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 643                                InstrStage<1, [A8_NLSPipe]>,
 644                                InstrStage<1, [A8_NPipe], 0>,
 645                                InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
 646   //
 647   // VTBX
 648   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 649                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
 650   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 651                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
 652   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 653                                InstrStage<1, [A8_NLSPipe]>,
 654                                InstrStage<1, [A8_NPipe], 0>,
 655                                InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
 656   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 657                                InstrStage<1, [A8_NLSPipe]>,
 658                                InstrStage<1, [A8_NPipe], 0>,
 659                             InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 660 ]>;