lib/Target/ARM/ARMScheduleA8.td

   1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 // Functional Units.
  17 def A8_Pipe0   : FuncUnit; // pipeline 0
  18 def A8_Pipe1   : FuncUnit; // pipeline 1
  19 def A8_LSPipe  : FuncUnit; // Load / store pipeline
  20 def A8_NPipe   : FuncUnit; // NEON ALU/MUL pipe
  21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
  22 //
  23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
  24 //
  25 def CortexA8Itineraries : ProcessorItineraries<
  26   [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
  27   [], [
  28   // Two fully-pipelined integer ALU pipelines
  29   //
  30   // No operand cycles
  31   InstrItinData<IIC_iALUx    , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
  32   //
  33   // Binary Instructions that produce a result
  34   InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  35   InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  36   InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  37   InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
  38   InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  39   //
  40   // Bitwise Instructions that produce a result
  41   InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  42   InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
  43   InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  44   InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
  45   //
  46   // Unary Instructions that produce a result
  47   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  48   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  49   //
  50   // Zero and sign extension instructions
  51   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  52   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
  53   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
  54   //
  55   // Compare instructions
  56   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  57   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  58   InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  59   InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  60   //
  61   // Test instructions
  62   InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  63   InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
  64   InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  65   InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  66   //
  67   // Move instructions, unconditional
  68   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  69   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  70   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  71   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  72   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
  73                              InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  74   //
  75   // Move instructions, conditional
  76   InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
  77   InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  78   InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
  79   InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
  80   //
  81   // MVN instructions
  82   InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
  83   InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  84   InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
  85   InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
  86
  87   // Integer multiply pipeline
  88   // Result written in E5, but that is relative to the last cycle of multicycle,
  89   // so we use 6 for those cases
  90   //
  91   InstrItinData<IIC_iMUL16   , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
  92   InstrItinData<IIC_iMAC16   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  93   InstrItinData<IIC_iMUL32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
  94   InstrItinData<IIC_iMAC32   , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
  95   InstrItinData<IIC_iMUL64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  96   InstrItinData<IIC_iMAC64   , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
  97
  98   // Integer load pipeline
  99   //
 100   // Immediate offset
 101   InstrItinData<IIC_iLoad_i   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 102                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 103   InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 104                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 105   InstrItinData<IIC_iLoad_d_i,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 106                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 107   //
 108   // Register offset
 109   InstrItinData<IIC_iLoad_r   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 110                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 111   InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 112                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 113   InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 114                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 115   //
 116   // Scaled register offset, issues over 2 cycles
 117   // FIXME: lsl by 2 takes 1 cycle.
 118   InstrItinData<IIC_iLoad_si  , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 119                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 120   InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 121                                  InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
 122   //
 123   // Immediate offset with update
 124   InstrItinData<IIC_iLoad_iu  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 125                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 126   InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 127                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
 128   //
 129   // Register offset with update
 130   InstrItinData<IIC_iLoad_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 131                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 132   InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 133                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 134   InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 135                                  InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
 136   //
 137   // Scaled register offset with update, issues over 2 cycles
 138   InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 139                                  InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
 140   InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 141                                   InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>,
 142   //
 143   // Load multiple, def is the 5th operand. Pipeline 0 only.
 144   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 145   InstrItinData<IIC_iLoad_m  , [InstrStage<2, [A8_Pipe0], 0>,
 146                                 InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
 147   //
 148   // Load multiple + update, defs are the 1st and 5th operands.
 149   InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>,
 150                                 InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
 151   //
 152   // Load multiple plus branch
 153   InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>,
 154                                 InstrStage<3, [A8_LSPipe]>,
 155                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 156                                [1, 2, 1, 1, 3]>,
 157   //
 158   // Pop, def is the 3rd operand.
 159   InstrItinData<IIC_iPop  ,    [InstrStage<3, [A8_Pipe0], 0>,
 160                                 InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
 161   //
 162   // Push, def is the 3th operand.
 163   InstrItinData<IIC_iPop_Br,   [InstrStage<3, [A8_Pipe0], 0>,
 164                                 InstrStage<3, [A8_LSPipe]>,
 165                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
 166                                [1, 1, 3]>,
 167
 168   //
 169   // iLoadi + iALUr for t2LDRpci_pic.
 170   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 171                                 InstrStage<1, [A8_LSPipe]>,
 172                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
 173
 174
 175   // Integer store pipeline
 176   //
 177   // Immediate offset
 178   InstrItinData<IIC_iStore_i  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 179                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 180   InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 181                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 182   InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 183                                  InstrStage<1, [A8_LSPipe]>], [3, 1]>,
 184   //
 185   // Register offset
 186   InstrItinData<IIC_iStore_r  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 187                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 188   InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 189                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 190   InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 191                                  InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
 192   //
 193   // Scaled register offset, issues over 2 cycles
 194   InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 195                                  InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 196   InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 197                                   InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
 198   //
 199   // Immediate offset with update
 200   InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 201                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 202   InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 203                                  InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
 204   //
 205   // Register offset with update
 206   InstrItinData<IIC_iStore_ru  , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 207                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 208   InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 209                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 210   InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 211                                   InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
 212   //
 213   // Scaled register offset with update, issues over 2 cycles
 214   InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 215                                  InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 216   InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>,
 217                                    InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
 218   //
 219   // Store multiple. Pipeline 0 only.
 220   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 221   InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>,
 222                                 InstrStage<2, [A8_LSPipe]>]>,
 223   //
 224   // Store multiple + update
 225   InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>,
 226                                 InstrStage<2, [A8_LSPipe]>], [2]>,
 227
 228   //
 229   // Preload
 230   InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
 231
 232   // Branch
 233   //
 234   // no delay slots, so the latency of a branch is unimportant
 235   InstrItinData<IIC_Br      , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 236
 237   // VFP
 238   // Issue through integer pipeline, and execute in NEON unit. We assume
 239   // RunFast mode so that NFP pipeline is used for single-precision when
 240   // possible.
 241   //
 242   // FP Special Register to Integer Register File Move
 243   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 244                               InstrStage<1, [A8_NLSPipe]>], [20]>,
 245   //
 246   // Single-precision FP Unary
 247   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 248                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 249   //
 250   // Double-precision FP Unary
 251   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 252                                InstrStage<4, [A8_NPipe], 0>,
 253                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 254   //
 255   // Single-precision FP Compare
 256   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 257                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 258   //
 259   // Double-precision FP Compare
 260   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 261                                InstrStage<4, [A8_NPipe], 0>,
 262                                InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
 263   //
 264   // Single to Double FP Convert
 265   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 266                                InstrStage<7, [A8_NPipe], 0>,
 267                                InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
 268   //
 269   // Double to Single FP Convert
 270   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 271                                InstrStage<5, [A8_NPipe], 0>,
 272                                InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
 273   //
 274   // Single-Precision FP to Integer Convert
 275   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 276                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 277   //
 278   // Double-Precision FP to Integer Convert
 279   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 280                                InstrStage<8, [A8_NPipe], 0>,
 281                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 282   //
 283   // Integer to Single-Precision FP Convert
 284   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 285                                InstrStage<1, [A8_NPipe]>], [7, 1]>,
 286   //
 287   // Integer to Double-Precision FP Convert
 288   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 289                                InstrStage<8, [A8_NPipe], 0>,
 290                                InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
 291   //
 292   // Single-precision FP ALU
 293   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 294                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 295   //
 296   // Double-precision FP ALU
 297   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 298                                InstrStage<9, [A8_NPipe], 0>,
 299                                InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
 300   //
 301   // Single-precision FP Multiply
 302   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 303                                InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
 304   //
 305   // Double-precision FP Multiply
 306   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 307                                InstrStage<11, [A8_NPipe], 0>,
 308                                InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
 309   //
 310   // Single-precision FP MAC
 311   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 312                                InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
 313   //
 314   // Double-precision FP MAC
 315   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 316                                InstrStage<19, [A8_NPipe], 0>,
 317                                InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
 318   //
 319   // Single-precision FP DIV
 320   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 321                                InstrStage<20, [A8_NPipe], 0>,
 322                                InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
 323   //
 324   // Double-precision FP DIV
 325   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 326                                InstrStage<29, [A8_NPipe], 0>,
 327                                InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
 328   //
 329   // Single-precision FP SQRT
 330   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 331                                InstrStage<19, [A8_NPipe], 0>,
 332                                InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
 333   //
 334   // Double-precision FP SQRT
 335   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 336                                InstrStage<29, [A8_NPipe], 0>,
 337                                InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
 338
 339   //
 340   // Integer to Single-precision Move
 341   InstrItinData<IIC_fpMOVIS,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 342                                InstrStage<1, [A8_NPipe]>],
 343                               [2, 1]>,
 344   //
 345   // Integer to Double-precision Move
 346   InstrItinData<IIC_fpMOVID,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 347                                InstrStage<1, [A8_NPipe]>],
 348                               [2, 1, 1]>,
 349   //
 350   // Single-precision to Integer Move
 351   InstrItinData<IIC_fpMOVSI,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 352                                InstrStage<1, [A8_NPipe]>],
 353                               [20, 1]>,
 354   //
 355   // Double-precision to Integer Move
 356   InstrItinData<IIC_fpMOVDI,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 357                                InstrStage<1, [A8_NPipe]>],
 358                               [20, 20, 1]>,
 359
 360   //
 361   // Single-precision FP Load
 362   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 363                                InstrStage<1, [A8_NLSPipe], 0>,
 364                                InstrStage<1, [A8_LSPipe]>],
 365                               [2, 1]>,
 366   //
 367   // Double-precision FP Load
 368   InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 369                                InstrStage<1, [A8_NLSPipe], 0>,
 370                                InstrStage<1, [A8_LSPipe]>],
 371                               [2, 1]>,
 372   //
 373   // FP Load Multiple
 374   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
 375   InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 376                                InstrStage<1, [A8_NLSPipe], 0>,
 377                                InstrStage<1, [A8_LSPipe]>,
 378                                InstrStage<1, [A8_NLSPipe], 0>,
 379                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
 380   //
 381   // FP Load Multiple + update
 382   InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 383                                InstrStage<1, [A8_NLSPipe], 0>,
 384                                InstrStage<1, [A8_LSPipe]>,
 385                                InstrStage<1, [A8_NLSPipe], 0>,
 386                                InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
 387   //
 388   // Single-precision FP Store
 389   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 390                                InstrStage<1, [A8_NLSPipe], 0>,
 391                                InstrStage<1, [A8_LSPipe]>],
 392                               [1, 1]>,
 393   //
 394   // Double-precision FP Store
 395   InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 396                                InstrStage<1, [A8_NLSPipe], 0>,
 397                                InstrStage<1, [A8_LSPipe]>],
 398                               [1, 1]>,
 399   //
 400   // FP Store Multiple
 401   InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 402                                InstrStage<1, [A8_NLSPipe], 0>,
 403                                InstrStage<1, [A8_LSPipe]>,
 404                                InstrStage<1, [A8_NLSPipe], 0>,
 405                                InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
 406   //
 407   // FP Store Multiple + update
 408   InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 409                                 InstrStage<1, [A8_NLSPipe], 0>,
 410                                 InstrStage<1, [A8_LSPipe]>,
 411                                 InstrStage<1, [A8_NLSPipe], 0>,
 412                                 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
 413
 414   // NEON
 415   // Issue through integer pipeline, and execute in NEON unit.
 416   //
 417   // VLD1
 418   InstrItinData<IIC_VLD1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 419                                InstrStage<2, [A8_NLSPipe], 0>,
 420                                InstrStage<2, [A8_LSPipe]>],
 421                               [2, 1]>,
 422   // VLD1x2
 423   InstrItinData<IIC_VLD1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 424                                InstrStage<2, [A8_NLSPipe], 0>,
 425                                InstrStage<2, [A8_LSPipe]>],
 426                               [2, 2, 1]>,
 427   //
 428   // VLD1x3
 429   InstrItinData<IIC_VLD1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 430                                InstrStage<3, [A8_NLSPipe], 0>,
 431                                InstrStage<3, [A8_LSPipe]>],
 432                               [2, 2, 3, 1]>,
 433   //
 434   // VLD1x4
 435   InstrItinData<IIC_VLD1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 436                                InstrStage<3, [A8_NLSPipe], 0>,
 437                                InstrStage<3, [A8_LSPipe]>],
 438                               [2, 2, 3, 3, 1]>,
 439   //
 440   // VLD1u
 441   InstrItinData<IIC_VLD1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 442                                InstrStage<2, [A8_NLSPipe], 0>,
 443                                InstrStage<2, [A8_LSPipe]>],
 444                               [2, 2, 1]>,
 445   //
 446   // VLD1x2u
 447   InstrItinData<IIC_VLD1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 448                                InstrStage<2, [A8_NLSPipe], 0>,
 449                                InstrStage<2, [A8_LSPipe]>],
 450                               [2, 2, 2, 1]>,
 451   //
 452   // VLD1x3u
 453   InstrItinData<IIC_VLD1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 454                                InstrStage<3, [A8_NLSPipe], 0>,
 455                                InstrStage<3, [A8_LSPipe]>],
 456                               [2, 2, 3, 2, 1]>,
 457   //
 458   // VLD1x4u
 459   InstrItinData<IIC_VLD1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 460                                InstrStage<3, [A8_NLSPipe], 0>,
 461                                InstrStage<3, [A8_LSPipe]>],
 462                               [2, 2, 3, 3, 2, 1]>,
 463   //
 464   // VLD1ln
 465   InstrItinData<IIC_VLD1ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 466                                InstrStage<3, [A8_NLSPipe], 1>,
 467                                InstrStage<3, [A8_LSPipe]>],
 468                               [3, 1, 1, 1]>,
 469   //
 470   // VLD1lnu
 471   InstrItinData<IIC_VLD1lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 472                                InstrStage<3, [A8_NLSPipe], 1>,
 473                                InstrStage<3, [A8_LSPipe]>],
 474                               [3, 2, 1, 1, 1, 1]>,
 475   //
 476   // VLD2
 477   InstrItinData<IIC_VLD2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 478                                InstrStage<2, [A8_NLSPipe], 0>,
 479                                InstrStage<2, [A8_LSPipe]>],
 480                               [2, 2, 1]>,
 481   //
 482   // VLD2x2
 483   InstrItinData<IIC_VLD2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 484                                InstrStage<3, [A8_NLSPipe], 0>,
 485                                InstrStage<3, [A8_LSPipe]>],
 486                               [2, 2, 3, 3, 1]>,
 487   //
 488   // VLD2ln
 489   InstrItinData<IIC_VLD2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 490                                InstrStage<3, [A8_NLSPipe], 0>,
 491                                InstrStage<3, [A8_LSPipe]>],
 492                               [3, 3, 1, 1, 1, 1]>,
 493   //
 494   // VLD2u
 495   InstrItinData<IIC_VLD2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 496                                InstrStage<2, [A8_NLSPipe], 0>,
 497                                InstrStage<2, [A8_LSPipe]>],
 498                               [2, 2, 2, 1, 1, 1]>,
 499   //
 500   // VLD2x2u
 501   InstrItinData<IIC_VLD2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 502                                InstrStage<3, [A8_NLSPipe], 0>,
 503                                InstrStage<3, [A8_LSPipe]>],
 504                               [2, 2, 3, 3, 2, 1]>,
 505   //
 506   // VLD2lnu
 507   InstrItinData<IIC_VLD2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 508                                InstrStage<3, [A8_NLSPipe], 0>,
 509                                InstrStage<3, [A8_LSPipe]>],
 510                               [3, 3, 2, 1, 1, 1, 1, 1]>,
 511   //
 512   // VLD3
 513   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 514                                InstrStage<4, [A8_NLSPipe], 0>,
 515                                InstrStage<4, [A8_LSPipe]>],
 516                               [3, 3, 4, 1]>,
 517   //
 518   // VLD3ln
 519   InstrItinData<IIC_VLD3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 520                                InstrStage<5, [A8_NLSPipe], 0>,
 521                                InstrStage<5, [A8_LSPipe]>],
 522                               [4, 4, 5, 1, 1, 1, 1, 2]>,
 523   //
 524   // VLD3u
 525   InstrItinData<IIC_VLD3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 526                                InstrStage<4, [A8_NLSPipe], 0>,
 527                                InstrStage<4, [A8_LSPipe]>],
 528                               [3, 3, 4, 2, 1]>,
 529   //
 530   // VLD3lnu
 531   InstrItinData<IIC_VLD3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 532                                InstrStage<5, [A8_NLSPipe], 0>,
 533                                InstrStage<5, [A8_LSPipe]>],
 534                               [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
 535   //
 536   // VLD4
 537   InstrItinData<IIC_VLD4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 538                                InstrStage<4, [A8_NLSPipe], 0>,
 539                                InstrStage<4, [A8_LSPipe]>],
 540                               [3, 3, 4, 4, 1]>,
 541   //
 542   // VLD4ln
 543   InstrItinData<IIC_VLD4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 544                                InstrStage<5, [A8_NLSPipe], 0>,
 545                                InstrStage<5, [A8_LSPipe]>],
 546                               [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
 547   //
 548   // VLD4u
 549   InstrItinData<IIC_VLD4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 550                                InstrStage<4, [A8_NLSPipe], 0>,
 551                                InstrStage<4, [A8_LSPipe]>],
 552                               [3, 3, 4, 4, 2, 1]>,
 553   //
 554   // VLD4lnu
 555   InstrItinData<IIC_VLD4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 556                                InstrStage<5, [A8_NLSPipe], 0>,
 557                                InstrStage<5, [A8_LSPipe]>],
 558                               [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
 559   //
 560   // VST1
 561   InstrItinData<IIC_VST1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 562                                InstrStage<2, [A8_NLSPipe], 0>,
 563                                InstrStage<2, [A8_LSPipe]>],
 564                               [1, 1, 1]>,
 565   //
 566   // VST1x2
 567   InstrItinData<IIC_VST1x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 568                                InstrStage<2, [A8_NLSPipe], 0>,
 569                                InstrStage<2, [A8_LSPipe]>],
 570                               [1, 1, 1, 1]>,
 571   //
 572   // VST1x3
 573   InstrItinData<IIC_VST1x3,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 574                                InstrStage<3, [A8_NLSPipe], 0>,
 575                                InstrStage<3, [A8_LSPipe]>],
 576                               [1, 1, 1, 1, 2]>,
 577   //
 578   // VST1x4
 579   InstrItinData<IIC_VST1x4,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 580                                InstrStage<3, [A8_NLSPipe], 0>,
 581                                InstrStage<3, [A8_LSPipe]>],
 582                               [1, 1, 1, 1, 2, 2]>,
 583   //
 584   // VST1u
 585   InstrItinData<IIC_VST1u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 586                                InstrStage<2, [A8_NLSPipe], 0>,
 587                                InstrStage<2, [A8_LSPipe]>],
 588                               [2, 1, 1, 1, 1]>,
 589   //
 590   // VST1x2u
 591   InstrItinData<IIC_VST1x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 592                                InstrStage<2, [A8_NLSPipe], 0>,
 593                                InstrStage<2, [A8_LSPipe]>],
 594                               [2, 1, 1, 1, 1, 1]>,
 595   //
 596   // VST1x3u
 597   InstrItinData<IIC_VST1x3u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 598                                InstrStage<3, [A8_NLSPipe], 0>,
 599                                InstrStage<3, [A8_LSPipe]>],
 600                               [2, 1, 1, 1, 1, 1, 2]>,
 601   //
 602   // VST1x4u
 603   InstrItinData<IIC_VST1x4u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 604                                InstrStage<3, [A8_NLSPipe], 0>,
 605                                InstrStage<3, [A8_LSPipe]>],
 606                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 607   //
 608   // VST1ln
 609   InstrItinData<IIC_VST1ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 610                                InstrStage<2, [A8_NLSPipe], 1>,
 611                                InstrStage<2, [A8_LSPipe]>],
 612                               [1, 1, 1]>,
 613   //
 614   // VST1lnu
 615   InstrItinData<IIC_VST1lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
 616                                InstrStage<2, [A8_NLSPipe], 1>,
 617                                InstrStage<2, [A8_LSPipe]>],
 618                               [2, 1, 1, 1, 1]>,
 619   //
 620   // VST2
 621   InstrItinData<IIC_VST2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 622                                InstrStage<2, [A8_NLSPipe], 0>,
 623                                InstrStage<2, [A8_LSPipe]>],
 624                               [1, 1, 1, 1]>,
 625   //
 626   // VST2x2
 627   InstrItinData<IIC_VST2x2,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 628                                InstrStage<4, [A8_NLSPipe], 0>,
 629                                InstrStage<4, [A8_LSPipe]>],
 630                               [1, 1, 1, 1, 2, 2]>,
 631   //
 632   // VST2u
 633   InstrItinData<IIC_VST2u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 634                                InstrStage<2, [A8_NLSPipe], 0>,
 635                                InstrStage<2, [A8_LSPipe]>],
 636                               [2, 1, 1, 1, 1, 1]>,
 637   //
 638   // VST2x2u
 639   InstrItinData<IIC_VST2x2u,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 640                                InstrStage<4, [A8_NLSPipe], 0>,
 641                                InstrStage<4, [A8_LSPipe]>],
 642                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 643   //
 644   // VST2ln
 645   InstrItinData<IIC_VST2ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 646                                InstrStage<2, [A8_NLSPipe], 0>,
 647                                InstrStage<2, [A8_LSPipe]>],
 648                               [1, 1, 1, 1]>,
 649   //
 650   // VST2lnu
 651   InstrItinData<IIC_VST2lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 652                                InstrStage<2, [A8_NLSPipe], 0>,
 653                                InstrStage<2, [A8_LSPipe]>],
 654                               [2, 1, 1, 1, 1, 1]>,
 655   //
 656   // VST3
 657   InstrItinData<IIC_VST3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 658                                InstrStage<3, [A8_NLSPipe], 0>,
 659                                InstrStage<3, [A8_LSPipe]>],
 660                               [1, 1, 1, 1, 2]>,
 661   //
 662   // VST3u
 663   InstrItinData<IIC_VST3u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 664                                InstrStage<3, [A8_NLSPipe], 0>,
 665                                InstrStage<3, [A8_LSPipe]>],
 666                               [2, 1, 1, 1, 1, 1, 2]>,
 667   //
 668   // VST3ln
 669   InstrItinData<IIC_VST3ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 670                                InstrStage<3, [A8_NLSPipe], 0>,
 671                                InstrStage<3, [A8_LSPipe]>],
 672                               [1, 1, 1, 1, 2]>,
 673   //
 674   // VST3lnu
 675   InstrItinData<IIC_VST3lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 676                                InstrStage<3, [A8_NLSPipe], 0>,
 677                                InstrStage<3, [A8_LSPipe]>],
 678                               [2, 1, 1, 1, 1, 1, 2]>,
 679   //
 680   // VST4
 681   InstrItinData<IIC_VST4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 682                                InstrStage<4, [A8_NLSPipe], 0>,
 683                                InstrStage<4, [A8_LSPipe]>],
 684                               [1, 1, 1, 1, 2, 2]>,
 685   //
 686   // VST4u
 687   InstrItinData<IIC_VST4u,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 688                                InstrStage<4, [A8_NLSPipe], 0>,
 689                                InstrStage<4, [A8_LSPipe]>],
 690                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 691   //
 692   // VST4ln
 693   InstrItinData<IIC_VST4ln,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 694                                InstrStage<4, [A8_NLSPipe], 0>,
 695                                InstrStage<4, [A8_LSPipe]>],
 696                               [1, 1, 1, 1, 2, 2]>,
 697   //
 698   // VST4lnu
 699   InstrItinData<IIC_VST4lnu,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 700                                InstrStage<4, [A8_NLSPipe], 0>,
 701                                InstrStage<4, [A8_LSPipe]>],
 702                               [2, 1, 1, 1, 1, 1, 2, 2]>,
 703   //
 704   // Double-register FP Unary
 705   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 706                                InstrStage<1, [A8_NPipe]>], [5, 2]>,
 707   //
 708   // Quad-register FP Unary
 709   // Result written in N5, but that is relative to the last cycle of multicycle,
 710   // so we use 6 for those cases
 711   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 712                                InstrStage<2, [A8_NPipe]>], [6, 2]>,
 713   //
 714   // Double-register FP Binary
 715   InstrItinData<IIC_VBIND,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 716                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 717   //
 718   // VPADD, etc.
 719   InstrItinData<IIC_VPBIND,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 720                                InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
 721   //
 722   // Double-register FP VMUL
 723   InstrItinData<IIC_VFMULD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 724                                InstrStage<1, [A8_NPipe]>], [5, 2, 1]>,
 725
 726   //
 727   // Quad-register FP Binary
 728   // Result written in N5, but that is relative to the last cycle of multicycle,
 729   // so we use 6 for those cases
 730   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 731                                InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
 732   //
 733   // Quad-register FP VMUL
 734   InstrItinData<IIC_VFMULQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 735                                InstrStage<1, [A8_NPipe]>], [6, 2, 1]>,
 736   //
 737   // Move
 738   InstrItinData<IIC_VMOV,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 739                                InstrStage<1, [A8_NPipe]>], [1, 1]>,
 740   //
 741   // Move Immediate
 742   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 743                                InstrStage<1, [A8_NPipe]>], [3]>,
 744   //
 745   // Double-register Permute Move
 746   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 747                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 748   //
 749   // Quad-register Permute Move
 750   // Result written in N2, but that is relative to the last cycle of multicycle,
 751   // so we use 3 for those cases
 752   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 753                                InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
 754   //
 755   // Integer to Single-precision Move
 756   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 757                                InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
 758   //
 759   // Integer to Double-precision Move
 760   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 761                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 762   //
 763   // Single-precision to Integer Move
 764   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 765                                InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
 766   //
 767   // Double-precision to Integer Move
 768   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 769                                InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
 770   //
 771   // Integer to Lane Move
 772   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 773                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 774   //
 775   // Vector narrow move
 776   InstrItinData<IIC_VMOVN   , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 777                                InstrStage<1, [A8_NPipe]>], [2, 1]>,
 778   //
 779   // Double-register Permute
 780   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 781                                InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
 782   //
 783   // Quad-register Permute
 784   // Result written in N2, but that is relative to the last cycle of multicycle,
 785   // so we use 3 for those cases
 786   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 787                                InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
 788   //
 789   // Quad-register Permute (3 cycle issue)
 790   // Result written in N2, but that is relative to the last cycle of multicycle,
 791   // so we use 4 for those cases
 792   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 793                                InstrStage<1, [A8_NLSPipe]>,
 794                                InstrStage<1, [A8_NPipe], 0>,
 795                                InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
 796   //
 797   // Double-register FP Multiple-Accumulate
 798   InstrItinData<IIC_VMACD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 799                                InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
 800   //
 801   // Quad-register FP Multiple-Accumulate
 802   // Result written in N9, but that is relative to the last cycle of multicycle,
 803   // so we use 10 for those cases
 804   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 805                                InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
 806   //
 807   // Double-register Reciprical Step
 808   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 809                                InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
 810   //
 811   // Quad-register Reciprical Step
 812   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 813                                InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
 814   //
 815   // Double-register Integer Count
 816   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 817                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 818   //
 819   // Quad-register Integer Count
 820   // Result written in N3, but that is relative to the last cycle of multicycle,
 821   // so we use 4 for those cases
 822   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 823                                InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
 824   //
 825   // Double-register Integer Unary
 826   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 827                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 828   //
 829   // Quad-register Integer Unary
 830   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 831                                InstrStage<1, [A8_NPipe]>], [4, 2]>,
 832   //
 833   // Double-register Integer Q-Unary
 834   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 835                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 836   //
 837   // Quad-register Integer CountQ-Unary
 838   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 839                                InstrStage<1, [A8_NPipe]>], [4, 1]>,
 840   //
 841   // Double-register Integer Binary
 842   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 843                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 844   //
 845   // Quad-register Integer Binary
 846   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 847                                InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
 848   //
 849   // Double-register Integer Binary (4 cycle)
 850   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 851                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 852   //
 853   // Quad-register Integer Binary (4 cycle)
 854   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 855                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 856
 857   //
 858   // Double-register Integer Subtract
 859   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 860                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 861   //
 862   // Quad-register Integer Subtract
 863   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 864                                InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
 865   //
 866   // Double-register Integer Subtract
 867   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 868                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 869   //
 870   // Quad-register Integer Subtract
 871   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 872                                InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
 873   //
 874   // Double-register Integer Shift
 875   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 876                                InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
 877   //
 878   // Quad-register Integer Shift
 879   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 880                                InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
 881   //
 882   // Double-register Integer Shift (4 cycle)
 883   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 884                                InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
 885   //
 886   // Quad-register Integer Shift (4 cycle)
 887   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 888                                InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
 889   //
 890   // Double-register Integer Pair Add Long
 891   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 892                                InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
 893   //
 894   // Quad-register Integer Pair Add Long
 895   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 896                                InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
 897   //
 898   // Double-register Absolute Difference and Accumulate
 899   InstrItinData<IIC_VABAD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 900                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
 901   //
 902   // Quad-register Absolute Difference and Accumulate
 903   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 904                                InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
 905
 906   //
 907   // Double-register Integer Multiply (.8, .16)
 908   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 909                                InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
 910   //
 911   // Double-register Integer Multiply (.32)
 912   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 913                                InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
 914   //
 915   // Quad-register Integer Multiply (.8, .16)
 916   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 917                                InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
 918   //
 919   // Quad-register Integer Multiply (.32)
 920   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 921                                InstrStage<1, [A8_NPipe]>,
 922                                InstrStage<2, [A8_NLSPipe], 0>,
 923                                InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
 924   //
 925   // Double-register Integer Multiply-Accumulate (.8, .16)
 926   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 927                                InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
 928   //
 929   // Double-register Integer Multiply-Accumulate (.32)
 930   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 931                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
 932   //
 933   // Quad-register Integer Multiply-Accumulate (.8, .16)
 934   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 935                                InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
 936   //
 937   // Quad-register Integer Multiply-Accumulate (.32)
 938   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 939                                InstrStage<1, [A8_NPipe]>,
 940                                InstrStage<2, [A8_NLSPipe], 0>,
 941                                InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
 942   //
 943   // Double-register VEXT
 944   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 945                                InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
 946   //
 947   // Quad-register VEXT
 948   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 949                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
 950   //
 951   // VTB
 952   InstrItinData<IIC_VTB1,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 953                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
 954   InstrItinData<IIC_VTB2,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 955                                InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
 956   InstrItinData<IIC_VTB3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 957                                InstrStage<1, [A8_NLSPipe]>,
 958                                InstrStage<1, [A8_NPipe], 0>,
 959                                InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
 960   InstrItinData<IIC_VTB4,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 961                                InstrStage<1, [A8_NLSPipe]>,
 962                                InstrStage<1, [A8_NPipe], 0>,
 963                                InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
 964   //
 965   // VTBX
 966   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 967                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
 968   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 969                                InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
 970   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 971                                InstrStage<1, [A8_NLSPipe]>,
 972                                InstrStage<1, [A8_NPipe], 0>,
 973                                InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
 974   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
 975                                InstrStage<1, [A8_NLSPipe]>,
 976                                InstrStage<1, [A8_NPipe], 0>,
 977                             InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 978 ]>;