1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
12 //===----------------------------------------------------------------------===//
15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
17 def A8_Issue : FuncUnit; // issue
18 def A8_Pipe0 : FuncUnit; // pipeline 0
19 def A8_Pipe1 : FuncUnit; // pipeline 1
20 def A8_LdSt0 : FuncUnit; // pipeline 0 load/store
21 def A8_LdSt1 : FuncUnit; // pipeline 1 load/store
22 def A8_NPipe : FuncUnit; // NEON ALU/MUL pipe
23 def A8_NLSPipe : FuncUnit; // NEON LS pipe
25 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
27 def CortexA8Itineraries : ProcessorItineraries<
28 [A8_Issue, A8_Pipe0, A8_Pipe1, A8_LdSt0, A8_LdSt1, A8_NPipe, A8_NLSPipe], [
29 // Two fully-pipelined integer ALU pipelines
32 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
34 // Binary Instructions that produce a result
35 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
36 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
37 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
40 // Unary Instructions that produce a result
41 InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
42 InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
43 InstrItinData<IIC_iUNAsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
45 // Zero and sign extension instructions
46 InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
47 InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
49 // Compare instructions
50 InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
51 InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
52 InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
53 InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
55 // Move instructions, unconditional
56 InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
57 InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
58 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
59 InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
60 InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
61 InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
63 // Move instructions, conditional
64 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
65 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
66 InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
67 InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
69 // Integer multiply pipeline
70 // Result written in E5, but that is relative to the last cycle of multicycle,
71 // so we use 6 for those cases
73 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
74 InstrItinData<IIC_iMAC16 , [InstrStage<1, [A8_Pipe1], 0>,
75 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
76 InstrItinData<IIC_iMUL32 , [InstrStage<1, [A8_Pipe1], 0>,
77 InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
78 InstrItinData<IIC_iMAC32 , [InstrStage<1, [A8_Pipe1], 0>,
79 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
80 InstrItinData<IIC_iMUL64 , [InstrStage<2, [A8_Pipe1], 0>,
81 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
82 InstrItinData<IIC_iMAC64 , [InstrStage<2, [A8_Pipe1], 0>,
83 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
85 // Integer load pipeline
87 // loads have an extra cycle of latency, but are fully pipelined
88 // use A8_Issue to enforce the 1 load/store per cycle limit
91 InstrItinData<IIC_iLoadi , [InstrStage<1, [A8_Issue], 0>,
92 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
93 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
96 InstrItinData<IIC_iLoadr , [InstrStage<1, [A8_Issue], 0>,
97 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
98 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
100 // Scaled register offset, issues over 2 cycles
101 InstrItinData<IIC_iLoadsi , [InstrStage<2, [A8_Issue], 0>,
102 InstrStage<1, [A8_Pipe0], 0>,
103 InstrStage<1, [A8_Pipe1]>,
104 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
105 InstrStage<1, [A8_LdSt0]>], [4, 1, 1]>,
107 // Immediate offset with update
108 InstrItinData<IIC_iLoadiu , [InstrStage<1, [A8_Issue], 0>,
109 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
110 InstrStage<1, [A8_LdSt0]>], [3, 2, 1]>,
112 // Register offset with update
113 InstrItinData<IIC_iLoadru , [InstrStage<1, [A8_Issue], 0>,
114 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
115 InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
117 // Scaled register offset with update, issues over 2 cycles
118 InstrItinData<IIC_iLoadsiu , [InstrStage<2, [A8_Issue], 0>,
119 InstrStage<1, [A8_Pipe0], 0>,
120 InstrStage<1, [A8_Pipe1]>,
121 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
122 InstrStage<1, [A8_LdSt0]>], [4, 3, 1, 1]>,
125 InstrItinData<IIC_iLoadm , [InstrStage<2, [A8_Issue], 0>,
126 InstrStage<2, [A8_Pipe0], 0>,
127 InstrStage<2, [A8_Pipe1]>,
128 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
129 InstrStage<1, [A8_LdSt0]>]>,
132 // Load multiple plus branch
133 InstrItinData<IIC_iLoadmBr , [InstrStage<2, [A8_Issue], 0>,
134 InstrStage<2, [A8_Pipe0], 0>,
135 InstrStage<2, [A8_Pipe1]>,
136 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
137 InstrStage<1, [A8_LdSt0]>,
138 InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
141 // iLoadi + iALUr for t2LDRpci_pic.
142 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Issue], 0>,
143 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
144 InstrStage<1, [A8_LdSt0]>,
145 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
148 // Integer store pipeline
150 // use A8_Issue to enforce the 1 load/store per cycle limit
153 InstrItinData<IIC_iStorei , [InstrStage<1, [A8_Issue], 0>,
154 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
155 InstrStage<1, [A8_LdSt0]>], [3, 1]>,
158 InstrItinData<IIC_iStorer , [InstrStage<1, [A8_Issue], 0>,
159 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
160 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
162 // Scaled register offset, issues over 2 cycles
163 InstrItinData<IIC_iStoresi , [InstrStage<2, [A8_Issue], 0>,
164 InstrStage<1, [A8_Pipe0], 0>,
165 InstrStage<1, [A8_Pipe1]>,
166 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
167 InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
169 // Immediate offset with update
170 InstrItinData<IIC_iStoreiu , [InstrStage<1, [A8_Issue], 0>,
171 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
172 InstrStage<1, [A8_LdSt0]>], [2, 3, 1]>,
174 // Register offset with update
175 InstrItinData<IIC_iStoreru , [InstrStage<1, [A8_Issue], 0>,
176 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
177 InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
179 // Scaled register offset with update, issues over 2 cycles
180 InstrItinData<IIC_iStoresiu, [InstrStage<2, [A8_Issue], 0>,
181 InstrStage<1, [A8_Pipe0], 0>,
182 InstrStage<1, [A8_Pipe1]>,
183 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
184 InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>,
187 InstrItinData<IIC_iStorem , [InstrStage<2, [A8_Issue], 0>,
188 InstrStage<2, [A8_Pipe0], 0>,
189 InstrStage<2, [A8_Pipe1]>,
190 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
191 InstrStage<1, [A8_LdSt0]>]>,
195 // no delay slots, so the latency of a branch is unimportant
196 InstrItinData<IIC_Br , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
199 // Issue through integer pipeline, and execute in NEON unit. We assume
200 // RunFast mode so that NFP pipeline is used for single-precision when
203 // FP Special Register to Integer Register File Move
204 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
205 InstrStage<1, [A8_NLSPipe]>]>,
207 // Single-precision FP Unary
208 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
209 InstrStage<1, [A8_NPipe]>], [7, 1]>,
211 // Double-precision FP Unary
212 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
213 InstrStage<4, [A8_NPipe], 0>,
214 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
216 // Single-precision FP Compare
217 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
218 InstrStage<1, [A8_NPipe]>], [1, 1]>,
220 // Double-precision FP Compare
221 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
222 InstrStage<4, [A8_NPipe], 0>,
223 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
225 // Single to Double FP Convert
226 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
227 InstrStage<7, [A8_NPipe], 0>,
228 InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
230 // Double to Single FP Convert
231 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
232 InstrStage<5, [A8_NPipe], 0>,
233 InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
235 // Single-Precision FP to Integer Convert
236 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
237 InstrStage<1, [A8_NPipe]>], [7, 1]>,
239 // Double-Precision FP to Integer Convert
240 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
241 InstrStage<8, [A8_NPipe], 0>,
242 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
244 // Integer to Single-Precision FP Convert
245 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
246 InstrStage<1, [A8_NPipe]>], [7, 1]>,
248 // Integer to Double-Precision FP Convert
249 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
250 InstrStage<8, [A8_NPipe], 0>,
251 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
253 // Single-precision FP ALU
254 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
255 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
257 // Double-precision FP ALU
258 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
259 InstrStage<9, [A8_NPipe], 0>,
260 InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
262 // Single-precision FP Multiply
263 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
264 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
266 // Double-precision FP Multiply
267 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
268 InstrStage<11, [A8_NPipe], 0>,
269 InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
271 // Single-precision FP MAC
272 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
273 InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
275 // Double-precision FP MAC
276 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
277 InstrStage<19, [A8_NPipe], 0>,
278 InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
280 // Single-precision FP DIV
281 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
282 InstrStage<20, [A8_NPipe], 0>,
283 InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
285 // Double-precision FP DIV
286 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
287 InstrStage<29, [A8_NPipe], 0>,
288 InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
290 // Single-precision FP SQRT
291 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
292 InstrStage<19, [A8_NPipe], 0>,
293 InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
295 // Double-precision FP SQRT
296 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
297 InstrStage<29, [A8_NPipe], 0>,
298 InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
300 // Single-precision FP Load
301 // use A8_Issue to enforce the 1 load/store per cycle limit
302 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>,
303 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
304 InstrStage<1, [A8_LdSt0], 0>,
305 InstrStage<1, [A8_NLSPipe]>]>,
307 // Double-precision FP Load
308 // use A8_Issue to enforce the 1 load/store per cycle limit
309 InstrItinData<IIC_fpLoad64, [InstrStage<2, [A8_Issue], 0>,
310 InstrStage<1, [A8_Pipe0], 0>,
311 InstrStage<1, [A8_Pipe1]>,
312 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
313 InstrStage<1, [A8_LdSt0], 0>,
314 InstrStage<1, [A8_NLSPipe]>]>,
317 // use A8_Issue to enforce the 1 load/store per cycle limit
318 InstrItinData<IIC_fpLoadm, [InstrStage<3, [A8_Issue], 0>,
319 InstrStage<2, [A8_Pipe0], 0>,
320 InstrStage<2, [A8_Pipe1]>,
321 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
322 InstrStage<1, [A8_LdSt0], 0>,
323 InstrStage<1, [A8_NLSPipe]>]>,
325 // Single-precision FP Store
326 // use A8_Issue to enforce the 1 load/store per cycle limit
327 InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>,
328 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
329 InstrStage<1, [A8_LdSt0], 0>,
330 InstrStage<1, [A8_NLSPipe]>]>,
332 // Double-precision FP Store
333 // use A8_Issue to enforce the 1 load/store per cycle limit
334 InstrItinData<IIC_fpStore64,[InstrStage<2, [A8_Issue], 0>,
335 InstrStage<1, [A8_Pipe0], 0>,
336 InstrStage<1, [A8_Pipe1]>,
337 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
338 InstrStage<1, [A8_LdSt0], 0>,
339 InstrStage<1, [A8_NLSPipe]>]>,
342 // use A8_Issue to enforce the 1 load/store per cycle limit
343 InstrItinData<IIC_fpStorem, [InstrStage<3, [A8_Issue], 0>,
344 InstrStage<2, [A8_Pipe0], 0>,
345 InstrStage<2, [A8_Pipe1]>,
346 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
347 InstrStage<1, [A8_LdSt0], 0>,
348 InstrStage<1, [A8_NLSPipe]>]>,
351 // Issue through integer pipeline, and execute in NEON unit.
354 // FIXME: We don't model this instruction properly
355 InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Issue], 0>,
356 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
357 InstrStage<1, [A8_LdSt0], 0>,
358 InstrStage<1, [A8_NLSPipe]>]>,
361 // FIXME: We don't model this instruction properly
362 InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Issue], 0>,
363 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
364 InstrStage<1, [A8_LdSt0], 0>,
365 InstrStage<1, [A8_NLSPipe]>], [2, 2, 1]>,
368 // FIXME: We don't model this instruction properly
369 InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Issue], 0>,
370 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
371 InstrStage<1, [A8_LdSt0], 0>,
372 InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 1]>,
375 // FIXME: We don't model this instruction properly
376 InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Issue], 0>,
377 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
378 InstrStage<1, [A8_LdSt0], 0>,
379 InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 2, 1]>,
382 // FIXME: We don't model this instruction properly
383 InstrItinData<IIC_VST, [InstrStage<1, [A8_Issue], 0>,
384 InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
385 InstrStage<1, [A8_LdSt0], 0>,
386 InstrStage<1, [A8_NLSPipe]>]>,
388 // Double-register FP Unary
389 InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
390 InstrStage<1, [A8_NPipe]>], [5, 2]>,
392 // Quad-register FP Unary
393 // Result written in N5, but that is relative to the last cycle of multicycle,
394 // so we use 6 for those cases
395 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
396 InstrStage<2, [A8_NPipe]>], [6, 2]>,
398 // Double-register FP Binary
399 InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
400 InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
402 // Quad-register FP Binary
403 // Result written in N5, but that is relative to the last cycle of multicycle,
404 // so we use 6 for those cases
405 InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
406 InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
409 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
410 InstrStage<1, [A8_NPipe]>], [3]>,
412 // Double-register Permute Move
413 InstrItinData<IIC_VMOVD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
414 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
416 // Quad-register Permute Move
417 // Result written in N2, but that is relative to the last cycle of multicycle,
418 // so we use 3 for those cases
419 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
420 InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
422 // Integer to Single-precision Move
423 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
424 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
426 // Integer to Double-precision Move
427 InstrItinData<IIC_VMOVID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
428 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
430 // Single-precision to Integer Move
431 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
432 InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
434 // Double-precision to Integer Move
435 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
436 InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
438 // Integer to Lane Move
439 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
440 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
442 // Double-register Permute
443 InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
444 InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
446 // Quad-register Permute
447 // Result written in N2, but that is relative to the last cycle of multicycle,
448 // so we use 3 for those cases
449 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
450 InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
452 // Quad-register Permute (3 cycle issue)
453 // Result written in N2, but that is relative to the last cycle of multicycle,
454 // so we use 4 for those cases
455 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
456 InstrStage<1, [A8_NLSPipe]>,
457 InstrStage<1, [A8_NPipe], 0>,
458 InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
460 // Double-register FP Multiple-Accumulate
461 InstrItinData<IIC_VMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
462 InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
464 // Quad-register FP Multiple-Accumulate
465 // Result written in N9, but that is relative to the last cycle of multicycle,
466 // so we use 10 for those cases
467 InstrItinData<IIC_VMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
468 InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
470 // Double-register Reciprical Step
471 InstrItinData<IIC_VRECSD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
472 InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
474 // Quad-register Reciprical Step
475 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
476 InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
478 // Double-register Integer Count
479 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
480 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
482 // Quad-register Integer Count
483 // Result written in N3, but that is relative to the last cycle of multicycle,
484 // so we use 4 for those cases
485 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
486 InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
488 // Double-register Integer Unary
489 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
490 InstrStage<1, [A8_NPipe]>], [4, 2]>,
492 // Quad-register Integer Unary
493 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
494 InstrStage<1, [A8_NPipe]>], [4, 2]>,
496 // Double-register Integer Q-Unary
497 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
498 InstrStage<1, [A8_NPipe]>], [4, 1]>,
500 // Quad-register Integer CountQ-Unary
501 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
502 InstrStage<1, [A8_NPipe]>], [4, 1]>,
504 // Double-register Integer Binary
505 InstrItinData<IIC_VBINiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
506 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
508 // Quad-register Integer Binary
509 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
510 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
512 // Double-register Integer Binary (4 cycle)
513 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
514 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
516 // Quad-register Integer Binary (4 cycle)
517 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
518 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
521 // Double-register Integer Subtract
522 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
523 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
525 // Quad-register Integer Subtract
526 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
527 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
529 // Double-register Integer Subtract
530 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
531 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
533 // Quad-register Integer Subtract
534 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
535 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
537 // Double-register Integer Shift
538 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
539 InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
541 // Quad-register Integer Shift
542 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
543 InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
545 // Double-register Integer Shift (4 cycle)
546 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
547 InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
549 // Quad-register Integer Shift (4 cycle)
550 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
551 InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
553 // Double-register Integer Pair Add Long
554 InstrItinData<IIC_VPALiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
555 InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
557 // Quad-register Integer Pair Add Long
558 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
559 InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
561 // Double-register Absolute Difference and Accumulate
562 InstrItinData<IIC_VABAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
563 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
565 // Quad-register Absolute Difference and Accumulate
566 InstrItinData<IIC_VABAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
567 InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
570 // Double-register Integer Multiply (.8, .16)
571 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
572 InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
574 // Double-register Integer Multiply (.32)
575 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
576 InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
578 // Quad-register Integer Multiply (.8, .16)
579 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
580 InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
582 // Quad-register Integer Multiply (.32)
583 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
584 InstrStage<1, [A8_NPipe]>,
585 InstrStage<2, [A8_NLSPipe], 0>,
586 InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
588 // Double-register Integer Multiply-Accumulate (.8, .16)
589 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
590 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
592 // Double-register Integer Multiply-Accumulate (.32)
593 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
594 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
596 // Quad-register Integer Multiply-Accumulate (.8, .16)
597 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
598 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
600 // Quad-register Integer Multiply-Accumulate (.32)
601 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
602 InstrStage<1, [A8_NPipe]>,
603 InstrStage<2, [A8_NLSPipe], 0>,
604 InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
606 // Double-register VEXT
607 InstrItinData<IIC_VEXTD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
608 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
610 // Quad-register VEXT
611 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
612 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
615 InstrItinData<IIC_VTB1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
616 InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
617 InstrItinData<IIC_VTB2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
618 InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
619 InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
620 InstrStage<1, [A8_NLSPipe]>,
621 InstrStage<1, [A8_NPipe], 0>,
622 InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
623 InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
624 InstrStage<1, [A8_NLSPipe]>,
625 InstrStage<1, [A8_NPipe], 0>,
626 InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
629 InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
630 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
631 InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
632 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
633 InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
634 InstrStage<1, [A8_NLSPipe]>,
635 InstrStage<1, [A8_NPipe], 0>,
636 InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
637 InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
638 InstrStage<1, [A8_NLSPipe]>,
639 InstrStage<1, [A8_NPipe], 0>,
640 InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>