1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM Cortex A8 processors.
12 //===----------------------------------------------------------------------===//
15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
17 def A8_Pipe0 : FuncUnit; // pipeline 0
18 def A8_Pipe1 : FuncUnit; // pipeline 1
19 def A8_LSPipe : FuncUnit; // Load / store pipeline
20 def A8_NPipe : FuncUnit; // NEON ALU/MUL pipe
21 def A8_NLSPipe : FuncUnit; // NEON LS pipe
23 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
25 def CortexA8Itineraries : ProcessorItineraries<
26 [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
28 // Two fully-pipelined integer ALU pipelines
31 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
33 // Binary Instructions that produce a result
34 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
35 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
36 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
37 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
40 // Bitwise Instructions that produce a result
41 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
42 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
43 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
44 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
46 // Unary Instructions that produce a result
47 InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
48 InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
50 // Zero and sign extension instructions
51 InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
52 InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
53 InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>,
55 // Compare instructions
56 InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
57 InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
58 InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
59 InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
62 InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
63 InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
64 InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
65 InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
67 // Move instructions, unconditional
68 InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
69 InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
70 InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
71 InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
72 InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
73 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
75 // Move instructions, conditional
76 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
77 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
78 InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
79 InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
82 InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
83 InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
84 InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
85 InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
87 // Integer multiply pipeline
88 // Result written in E5, but that is relative to the last cycle of multicycle,
89 // so we use 6 for those cases
91 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>,
92 InstrItinData<IIC_iMAC16 , [InstrStage<1, [A8_Pipe1], 0>,
93 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
94 InstrItinData<IIC_iMUL32 , [InstrStage<1, [A8_Pipe1], 0>,
95 InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>,
96 InstrItinData<IIC_iMAC32 , [InstrStage<1, [A8_Pipe1], 0>,
97 InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>,
98 InstrItinData<IIC_iMUL64 , [InstrStage<2, [A8_Pipe1], 0>,
99 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
100 InstrItinData<IIC_iMAC64 , [InstrStage<2, [A8_Pipe1], 0>,
101 InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>,
103 // Integer load pipeline
106 InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
107 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
108 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
109 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
110 InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
111 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
114 InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
115 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
116 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
117 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
118 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
119 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
121 // Scaled register offset, issues over 2 cycles
122 // FIXME: lsl by 2 takes 1 cycle.
123 InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
124 InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
125 InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
126 InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
128 // Immediate offset with update
129 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
130 InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
131 InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
132 InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
134 // Register offset with update
135 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
136 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
137 InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
138 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
139 InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
140 InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
142 // Scaled register offset with update, issues over 2 cycles
143 InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
144 InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>,
145 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
146 InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>,
148 // Load multiple, def is the 5th operand. Pipeline 0 only.
149 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
150 InstrItinData<IIC_iLoad_m , [InstrStage<1, [A8_Pipe0]>,
151 InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
153 // Load multiple + update, defs are the 1st and 5th operands.
154 InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A8_Pipe0]>,
155 InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
157 // Load multiple plus branch
158 InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A8_Pipe0]>,
159 InstrStage<3, [A8_LSPipe]>,
160 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
163 // Pop, def is the 3rd operand.
164 InstrItinData<IIC_iPop , [InstrStage<1, [A8_Pipe0]>,
165 InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
167 // Push, def is the 3th operand.
168 InstrItinData<IIC_iPop_Br, [InstrStage<1, [A8_Pipe0]>,
169 InstrStage<3, [A8_LSPipe]>,
170 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
174 // iLoadi + iALUr for t2LDRpci_pic.
175 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
176 InstrStage<1, [A8_LSPipe]>,
177 InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
180 // Integer store pipeline
183 InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
184 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
185 InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
186 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
187 InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
188 InstrStage<1, [A8_LSPipe]>], [3, 1]>,
191 InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
192 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
193 InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
194 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
195 InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
196 InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
198 // Scaled register offset, issues over 2 cycles
199 InstrItinData<IIC_iStore_si , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
200 InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
201 InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
202 InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
204 // Immediate offset with update
205 InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
206 InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
207 InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
208 InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
210 // Register offset with update
211 InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
212 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
213 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
214 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
215 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
216 InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
218 // Scaled register offset with update, issues over 2 cycles
219 InstrItinData<IIC_iStore_siu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
220 InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
221 InstrItinData<IIC_iStore_bh_siu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
222 InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
224 // Store multiple. Pipeline 0 only.
225 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
226 InstrItinData<IIC_iStore_m , [InstrStage<1, [A8_Pipe0]>,
227 InstrStage<2, [A8_LSPipe]>]>,
229 // Store multiple + update
230 InstrItinData<IIC_iStore_mu, [InstrStage<1, [A8_Pipe0]>,
231 InstrStage<2, [A8_LSPipe]>], [2]>,
235 // no delay slots, so the latency of a branch is unimportant
236 InstrItinData<IIC_Br , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
239 // Issue through integer pipeline, and execute in NEON unit. We assume
240 // RunFast mode so that NFP pipeline is used for single-precision when
243 // FP Special Register to Integer Register File Move
244 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
245 InstrStage<1, [A8_NLSPipe]>]>,
247 // Single-precision FP Unary
248 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
249 InstrStage<1, [A8_NPipe]>], [7, 1]>,
251 // Double-precision FP Unary
252 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
253 InstrStage<4, [A8_NPipe], 0>,
254 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
256 // Single-precision FP Compare
257 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
258 InstrStage<1, [A8_NPipe]>], [1, 1]>,
260 // Double-precision FP Compare
261 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
262 InstrStage<4, [A8_NPipe], 0>,
263 InstrStage<4, [A8_NLSPipe]>], [4, 1]>,
265 // Single to Double FP Convert
266 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
267 InstrStage<7, [A8_NPipe], 0>,
268 InstrStage<7, [A8_NLSPipe]>], [7, 1]>,
270 // Double to Single FP Convert
271 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
272 InstrStage<5, [A8_NPipe], 0>,
273 InstrStage<5, [A8_NLSPipe]>], [5, 1]>,
275 // Single-Precision FP to Integer Convert
276 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
277 InstrStage<1, [A8_NPipe]>], [7, 1]>,
279 // Double-Precision FP to Integer Convert
280 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
281 InstrStage<8, [A8_NPipe], 0>,
282 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
284 // Integer to Single-Precision FP Convert
285 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
286 InstrStage<1, [A8_NPipe]>], [7, 1]>,
288 // Integer to Double-Precision FP Convert
289 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
290 InstrStage<8, [A8_NPipe], 0>,
291 InstrStage<8, [A8_NLSPipe]>], [8, 1]>,
293 // Single-precision FP ALU
294 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
295 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
297 // Double-precision FP ALU
298 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
299 InstrStage<9, [A8_NPipe], 0>,
300 InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>,
302 // Single-precision FP Multiply
303 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
304 InstrStage<1, [A8_NPipe]>], [7, 1, 1]>,
306 // Double-precision FP Multiply
307 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
308 InstrStage<11, [A8_NPipe], 0>,
309 InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>,
311 // Single-precision FP MAC
312 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
313 InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>,
315 // Double-precision FP MAC
316 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
317 InstrStage<19, [A8_NPipe], 0>,
318 InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>,
320 // Single-precision FP DIV
321 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
322 InstrStage<20, [A8_NPipe], 0>,
323 InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>,
325 // Double-precision FP DIV
326 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
327 InstrStage<29, [A8_NPipe], 0>,
328 InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>,
330 // Single-precision FP SQRT
331 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
332 InstrStage<19, [A8_NPipe], 0>,
333 InstrStage<19, [A8_NLSPipe]>], [19, 1]>,
335 // Double-precision FP SQRT
336 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
337 InstrStage<29, [A8_NPipe], 0>,
338 InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
340 // Single-precision FP Load
341 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
342 InstrStage<1, [A8_NLSPipe]>,
343 InstrStage<1, [A8_LSPipe]>],
346 // Double-precision FP Load
347 InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
348 InstrStage<1, [A8_NLSPipe]>,
349 InstrStage<1, [A8_LSPipe]>],
353 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
354 InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
355 InstrStage<1, [A8_NLSPipe]>,
356 InstrStage<1, [A8_LSPipe]>,
357 InstrStage<1, [A8_NLSPipe]>,
358 InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
360 // FP Load Multiple + update
361 InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
362 InstrStage<1, [A8_NLSPipe]>,
363 InstrStage<1, [A8_LSPipe]>,
364 InstrStage<1, [A8_NLSPipe]>,
365 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
367 // Single-precision FP Store
368 InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
369 InstrStage<1, [A8_NLSPipe]>,
370 InstrStage<1, [A8_LSPipe]>],
373 // Double-precision FP Store
374 InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
375 InstrStage<1, [A8_NLSPipe]>,
376 InstrStage<1, [A8_LSPipe]>],
380 InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
381 InstrStage<1, [A8_NLSPipe]>,
382 InstrStage<1, [A8_LSPipe]>,
383 InstrStage<1, [A8_NLSPipe]>,
384 InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
386 // FP Store Multiple + update
387 InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
388 InstrStage<1, [A8_NLSPipe]>,
389 InstrStage<1, [A8_LSPipe]>,
390 InstrStage<1, [A8_NLSPipe]>,
391 InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
394 // Issue through integer pipeline, and execute in NEON unit.
397 InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
398 InstrStage<1, [A8_NLSPipe]>,
399 InstrStage<1, [A8_LSPipe]>]>,
401 InstrItinData<IIC_VLD1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
402 InstrStage<2, [A8_NLSPipe], 1>,
403 InstrStage<2, [A8_LSPipe]>],
407 InstrItinData<IIC_VLD1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
408 InstrStage<3, [A8_NLSPipe], 1>,
409 InstrStage<3, [A8_LSPipe]>],
413 InstrItinData<IIC_VLD1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
414 InstrStage<3, [A8_NLSPipe], 1>,
415 InstrStage<3, [A8_LSPipe]>],
419 InstrItinData<IIC_VLD1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
420 InstrStage<1, [A8_NLSPipe]>,
421 InstrStage<1, [A8_LSPipe]>],
425 InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
426 InstrStage<2, [A8_NLSPipe], 1>,
427 InstrStage<2, [A8_LSPipe]>],
431 InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
432 InstrStage<3, [A8_NLSPipe], 1>,
433 InstrStage<3, [A8_LSPipe]>],
437 InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
438 InstrStage<3, [A8_NLSPipe], 1>,
439 InstrStage<3, [A8_LSPipe]>],
443 InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
444 InstrStage<1, [A8_NLSPipe]>,
445 InstrStage<1, [A8_LSPipe]>], [2, 2, 1]>,
448 InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
449 InstrStage<1, [A8_NLSPipe]>,
450 InstrStage<1, [A8_LSPipe]>], [2, 2, 2, 1]>,
453 InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
454 InstrStage<1, [A8_NLSPipe]>,
455 InstrStage<1, [A8_LSPipe]>], [2, 2, 2, 2, 1]>,
458 // FIXME: We don't model this instruction properly
459 InstrItinData<IIC_VST, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
460 InstrStage<1, [A8_NLSPipe]>,
461 InstrStage<1, [A8_LSPipe]>]>,
463 // Double-register FP Unary
464 InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
465 InstrStage<1, [A8_NPipe]>], [5, 2]>,
467 // Quad-register FP Unary
468 // Result written in N5, but that is relative to the last cycle of multicycle,
469 // so we use 6 for those cases
470 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
471 InstrStage<2, [A8_NPipe]>], [6, 2]>,
473 // Double-register FP Binary
474 InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
475 InstrStage<1, [A8_NPipe]>], [5, 2, 2]>,
477 // Quad-register FP Binary
478 // Result written in N5, but that is relative to the last cycle of multicycle,
479 // so we use 6 for those cases
480 InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
481 InstrStage<2, [A8_NPipe]>], [6, 2, 2]>,
484 InstrItinData<IIC_VMOV, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
485 InstrStage<1, [A8_NPipe]>], [1, 1]>,
488 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
489 InstrStage<1, [A8_NPipe]>], [3]>,
491 // Double-register Permute Move
492 InstrItinData<IIC_VMOVD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
493 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
495 // Quad-register Permute Move
496 // Result written in N2, but that is relative to the last cycle of multicycle,
497 // so we use 3 for those cases
498 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
499 InstrStage<2, [A8_NLSPipe]>], [3, 1]>,
501 // Integer to Single-precision Move
502 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
503 InstrStage<1, [A8_NLSPipe]>], [2, 1]>,
505 // Integer to Double-precision Move
506 InstrItinData<IIC_VMOVID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
507 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
509 // Single-precision to Integer Move
510 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
511 InstrStage<1, [A8_NLSPipe]>], [20, 1]>,
513 // Double-precision to Integer Move
514 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
515 InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>,
517 // Integer to Lane Move
518 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
519 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
521 // Vector narrow move
522 InstrItinData<IIC_VMOVN , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
523 InstrStage<1, [A8_NPipe]>], [2, 1]>,
525 // Double-register Permute
526 InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
527 InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>,
529 // Quad-register Permute
530 // Result written in N2, but that is relative to the last cycle of multicycle,
531 // so we use 3 for those cases
532 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
533 InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>,
535 // Quad-register Permute (3 cycle issue)
536 // Result written in N2, but that is relative to the last cycle of multicycle,
537 // so we use 4 for those cases
538 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
539 InstrStage<1, [A8_NLSPipe]>,
540 InstrStage<1, [A8_NPipe], 0>,
541 InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>,
543 // Double-register FP Multiple-Accumulate
544 InstrItinData<IIC_VMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
545 InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>,
547 // Quad-register FP Multiple-Accumulate
548 // Result written in N9, but that is relative to the last cycle of multicycle,
549 // so we use 10 for those cases
550 InstrItinData<IIC_VMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
551 InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>,
553 // Double-register Reciprical Step
554 InstrItinData<IIC_VRECSD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
555 InstrStage<1, [A8_NPipe]>], [9, 2, 2]>,
557 // Quad-register Reciprical Step
558 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
559 InstrStage<2, [A8_NPipe]>], [10, 2, 2]>,
561 // Double-register Integer Count
562 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
563 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
565 // Quad-register Integer Count
566 // Result written in N3, but that is relative to the last cycle of multicycle,
567 // so we use 4 for those cases
568 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
569 InstrStage<2, [A8_NPipe]>], [4, 2, 2]>,
571 // Double-register Integer Unary
572 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
573 InstrStage<1, [A8_NPipe]>], [4, 2]>,
575 // Quad-register Integer Unary
576 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
577 InstrStage<1, [A8_NPipe]>], [4, 2]>,
579 // Double-register Integer Q-Unary
580 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
581 InstrStage<1, [A8_NPipe]>], [4, 1]>,
583 // Quad-register Integer CountQ-Unary
584 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
585 InstrStage<1, [A8_NPipe]>], [4, 1]>,
587 // Double-register Integer Binary
588 InstrItinData<IIC_VBINiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
589 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
591 // Quad-register Integer Binary
592 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
593 InstrStage<1, [A8_NPipe]>], [3, 2, 2]>,
595 // Double-register Integer Binary (4 cycle)
596 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
597 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
599 // Quad-register Integer Binary (4 cycle)
600 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
601 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
604 // Double-register Integer Subtract
605 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
606 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
608 // Quad-register Integer Subtract
609 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
610 InstrStage<1, [A8_NPipe]>], [3, 2, 1]>,
612 // Double-register Integer Subtract
613 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
614 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
616 // Quad-register Integer Subtract
617 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
618 InstrStage<1, [A8_NPipe]>], [4, 2, 1]>,
620 // Double-register Integer Shift
621 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
622 InstrStage<1, [A8_NPipe]>], [3, 1, 1]>,
624 // Quad-register Integer Shift
625 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
626 InstrStage<2, [A8_NPipe]>], [4, 1, 1]>,
628 // Double-register Integer Shift (4 cycle)
629 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
630 InstrStage<1, [A8_NPipe]>], [4, 1, 1]>,
632 // Quad-register Integer Shift (4 cycle)
633 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
634 InstrStage<2, [A8_NPipe]>], [5, 1, 1]>,
636 // Double-register Integer Pair Add Long
637 InstrItinData<IIC_VPALiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
638 InstrStage<1, [A8_NPipe]>], [6, 3, 1]>,
640 // Quad-register Integer Pair Add Long
641 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
642 InstrStage<2, [A8_NPipe]>], [7, 3, 1]>,
644 // Double-register Absolute Difference and Accumulate
645 InstrItinData<IIC_VABAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
646 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>,
648 // Quad-register Absolute Difference and Accumulate
649 InstrItinData<IIC_VABAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
650 InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>,
653 // Double-register Integer Multiply (.8, .16)
654 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
655 InstrStage<1, [A8_NPipe]>], [6, 2, 2]>,
657 // Double-register Integer Multiply (.32)
658 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
659 InstrStage<2, [A8_NPipe]>], [7, 2, 1]>,
661 // Quad-register Integer Multiply (.8, .16)
662 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
663 InstrStage<2, [A8_NPipe]>], [7, 2, 2]>,
665 // Quad-register Integer Multiply (.32)
666 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
667 InstrStage<1, [A8_NPipe]>,
668 InstrStage<2, [A8_NLSPipe], 0>,
669 InstrStage<3, [A8_NPipe]>], [9, 2, 1]>,
671 // Double-register Integer Multiply-Accumulate (.8, .16)
672 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
673 InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>,
675 // Double-register Integer Multiply-Accumulate (.32)
676 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
677 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>,
679 // Quad-register Integer Multiply-Accumulate (.8, .16)
680 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
681 InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>,
683 // Quad-register Integer Multiply-Accumulate (.32)
684 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
685 InstrStage<1, [A8_NPipe]>,
686 InstrStage<2, [A8_NLSPipe], 0>,
687 InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>,
689 // Double-register VEXT
690 InstrItinData<IIC_VEXTD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
691 InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>,
693 // Quad-register VEXT
694 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
695 InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>,
698 InstrItinData<IIC_VTB1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
699 InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>,
700 InstrItinData<IIC_VTB2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
701 InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>,
702 InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
703 InstrStage<1, [A8_NLSPipe]>,
704 InstrStage<1, [A8_NPipe], 0>,
705 InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>,
706 InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
707 InstrStage<1, [A8_NLSPipe]>,
708 InstrStage<1, [A8_NPipe], 0>,
709 InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>,
712 InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
713 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>,
714 InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
715 InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>,
716 InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
717 InstrStage<1, [A8_NLSPipe]>,
718 InstrStage<1, [A8_NPipe], 0>,
719 InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>,
720 InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
721 InstrStage<1, [A8_NLSPipe]>,
722 InstrStage<1, [A8_NPipe], 0>,
723 InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>