1 //=- ARMScheduleA9.td - ARM Cortex-A9 Scheduling Definitions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM Cortex A9 processors.
12 //===----------------------------------------------------------------------===//
15 // Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
19 def A9_Issue0 : FuncUnit; // Issue 0
20 def A9_Issue1 : FuncUnit; // Issue 1
21 def A9_Branch : FuncUnit; // Branch
22 def A9_ALU0 : FuncUnit; // ALU / MUL pipeline 0
23 def A9_ALU1 : FuncUnit; // ALU pipeline 1
24 def A9_AGU : FuncUnit; // Address generation unit for ld / st
25 def A9_NPipe : FuncUnit; // NEON pipeline
26 def A9_MUX0 : FuncUnit; // AGU + NEON/FPU multiplexer
27 def A9_LSUnit : FuncUnit; // L/S Unit
28 def A9_DRegsVFP: FuncUnit; // FP register set, VFP side
29 def A9_DRegsN : FuncUnit; // FP register set, NEON side
32 def A9_LdBypass : Bypass;
34 def CortexA9Itineraries : ProcessorItineraries<
35 [A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0,
36 A9_LSUnit, A9_DRegsVFP, A9_DRegsN],
38 // Two fully-pipelined integer ALU pipelines
41 // Move instructions, unconditional
42 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
43 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
44 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
45 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
46 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
47 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
48 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
49 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
50 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
51 InstrStage<1, [A9_ALU0, A9_ALU1]>,
52 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>,
53 InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
54 InstrStage<1, [A9_ALU0, A9_ALU1]>,
55 InstrStage<1, [A9_ALU0, A9_ALU1]>,
56 InstrStage<1, [A9_ALU0, A9_ALU1]>], [3]>,
57 InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
58 InstrStage<1, [A9_ALU0, A9_ALU1]>,
59 InstrStage<1, [A9_ALU0, A9_ALU1]>,
60 InstrStage<1, [A9_MUX0], 0>,
61 InstrStage<1, [A9_AGU], 0>,
62 InstrStage<1, [A9_LSUnit]>], [5]>,
65 InstrItinData<IIC_iMVNi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
66 InstrStage<1, [A9_ALU0, A9_ALU1]>],
68 InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
69 InstrStage<1, [A9_ALU0, A9_ALU1]>],
70 [1, 1], [NoBypass, A9_LdBypass]>,
71 InstrItinData<IIC_iMVNsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
72 InstrStage<2, [A9_ALU0, A9_ALU1]>],
74 InstrItinData<IIC_iMVNsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
75 InstrStage<3, [A9_ALU0, A9_ALU1]>],
79 InstrItinData<IIC_iALUx , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
80 InstrStage<1, [A9_ALU0, A9_ALU1]>]>,
82 // Binary Instructions that produce a result
83 InstrItinData<IIC_iALUi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
84 InstrStage<1, [A9_ALU0, A9_ALU1]>],
85 [1, 1], [NoBypass, A9_LdBypass]>,
86 InstrItinData<IIC_iALUr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
87 InstrStage<1, [A9_ALU0, A9_ALU1]>],
88 [1, 1, 1], [NoBypass, A9_LdBypass, A9_LdBypass]>,
89 InstrItinData<IIC_iALUsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
90 InstrStage<2, [A9_ALU0, A9_ALU1]>],
91 [2, 1, 1], [NoBypass, A9_LdBypass, NoBypass]>,
92 InstrItinData<IIC_iALUsir,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
93 InstrStage<2, [A9_ALU0, A9_ALU1]>],
94 [2, 1, 1], [NoBypass, NoBypass, A9_LdBypass]>,
95 InstrItinData<IIC_iALUsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
96 InstrStage<3, [A9_ALU0, A9_ALU1]>],
98 [NoBypass, A9_LdBypass, NoBypass, NoBypass]>,
100 // Bitwise Instructions that produce a result
101 InstrItinData<IIC_iBITi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
102 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
103 InstrItinData<IIC_iBITr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
104 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
105 InstrItinData<IIC_iBITsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
106 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
107 InstrItinData<IIC_iBITsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
108 InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
110 // Unary Instructions that produce a result
113 InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
114 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
116 // BFC, BFI, UBFX, SBFX
117 InstrItinData<IIC_iUNAsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
118 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1]>,
121 // Zero and sign extension instructions
122 InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
123 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2, 1]>,
124 InstrItinData<IIC_iEXTAr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
125 InstrStage<2, [A9_ALU0, A9_ALU1]>], [3, 1, 1]>,
126 InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
127 InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
129 // Compare instructions
130 InstrItinData<IIC_iCMPi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
131 InstrStage<1, [A9_ALU0, A9_ALU1]>],
133 InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
134 InstrStage<1, [A9_ALU0, A9_ALU1]>],
135 [1, 1], [A9_LdBypass, A9_LdBypass]>,
136 InstrItinData<IIC_iCMPsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
137 InstrStage<2, [A9_ALU0, A9_ALU1]>],
138 [1, 1], [A9_LdBypass, NoBypass]>,
139 InstrItinData<IIC_iCMPsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
140 InstrStage<3, [A9_ALU0, A9_ALU1]>],
141 [1, 1, 1], [A9_LdBypass, NoBypass, NoBypass]>,
144 InstrItinData<IIC_iTSTi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
145 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
146 InstrItinData<IIC_iTSTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
147 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
148 InstrItinData<IIC_iTSTsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
149 InstrStage<2, [A9_ALU0, A9_ALU1]>], [1, 1]>,
150 InstrItinData<IIC_iTSTsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
151 InstrStage<3, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
153 // Move instructions, conditional
154 // FIXME: Correctly model the extra input dep on the destination.
155 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
156 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
157 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
158 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
159 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
160 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
161 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
162 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
163 InstrItinData<IIC_iCMOVix2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
164 InstrStage<1, [A9_ALU0, A9_ALU1]>,
165 InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
166 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>,
168 // Integer multiply pipeline
170 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
171 InstrStage<2, [A9_ALU0]>], [3, 1, 1]>,
172 InstrItinData<IIC_iMAC16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
173 InstrStage<2, [A9_ALU0]>],
175 InstrItinData<IIC_iMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
176 InstrStage<2, [A9_ALU0]>], [4, 1, 1]>,
177 InstrItinData<IIC_iMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
178 InstrStage<2, [A9_ALU0]>],
180 InstrItinData<IIC_iMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
181 InstrStage<3, [A9_ALU0]>], [4, 5, 1, 1]>,
182 InstrItinData<IIC_iMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
183 InstrStage<3, [A9_ALU0]>],
185 // Integer load pipeline
186 // FIXME: The timings are some rough approximations
189 InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
190 InstrStage<1, [A9_MUX0], 0>,
191 InstrStage<1, [A9_AGU], 0>,
192 InstrStage<1, [A9_LSUnit]>],
193 [3, 1], [A9_LdBypass]>,
194 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
195 InstrStage<1, [A9_MUX0], 0>,
196 InstrStage<2, [A9_AGU], 0>,
197 InstrStage<1, [A9_LSUnit]>],
198 [4, 1], [A9_LdBypass]>,
199 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
200 InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
201 InstrStage<1, [A9_MUX0], 0>,
202 InstrStage<2, [A9_AGU], 0>,
203 InstrStage<1, [A9_LSUnit]>],
204 [3, 3, 1], [A9_LdBypass]>,
207 InstrItinData<IIC_iLoad_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
208 InstrStage<1, [A9_MUX0], 0>,
209 InstrStage<1, [A9_AGU], 0>,
210 InstrStage<1, [A9_LSUnit]>],
211 [3, 1, 1], [A9_LdBypass]>,
212 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
213 InstrStage<1, [A9_MUX0], 0>,
214 InstrStage<2, [A9_AGU], 0>,
215 InstrStage<1, [A9_LSUnit]>],
216 [4, 1, 1], [A9_LdBypass]>,
217 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
218 InstrStage<1, [A9_MUX0], 0>,
219 InstrStage<2, [A9_AGU], 0>,
220 InstrStage<1, [A9_LSUnit]>],
221 [3, 3, 1, 1], [A9_LdBypass]>,
223 // Scaled register offset
224 InstrItinData<IIC_iLoad_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
225 InstrStage<1, [A9_MUX0], 0>,
226 InstrStage<1, [A9_AGU], 0>,
227 InstrStage<1, [A9_LSUnit], 0>],
228 [4, 1, 1], [A9_LdBypass]>,
229 InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
230 InstrStage<1, [A9_MUX0], 0>,
231 InstrStage<2, [A9_AGU], 0>,
232 InstrStage<1, [A9_LSUnit]>],
233 [5, 1, 1], [A9_LdBypass]>,
235 // Immediate offset with update
236 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
237 InstrStage<1, [A9_MUX0], 0>,
238 InstrStage<1, [A9_AGU], 0>,
239 InstrStage<1, [A9_LSUnit]>],
240 [3, 2, 1], [A9_LdBypass]>,
241 InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
242 InstrStage<1, [A9_MUX0], 0>,
243 InstrStage<2, [A9_AGU], 0>,
244 InstrStage<1, [A9_LSUnit]>],
245 [4, 3, 1], [A9_LdBypass]>,
247 // Register offset with update
248 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
249 InstrStage<1, [A9_MUX0], 0>,
250 InstrStage<1, [A9_AGU], 0>,
251 InstrStage<1, [A9_LSUnit]>],
252 [3, 2, 1, 1], [A9_LdBypass]>,
253 InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
254 InstrStage<1, [A9_MUX0], 0>,
255 InstrStage<2, [A9_AGU], 0>,
256 InstrStage<1, [A9_LSUnit]>],
257 [4, 3, 1, 1], [A9_LdBypass]>,
258 InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
259 InstrStage<1, [A9_MUX0], 0>,
260 InstrStage<2, [A9_AGU], 0>,
261 InstrStage<1, [A9_LSUnit]>],
262 [3, 3, 1, 1], [A9_LdBypass]>,
264 // Scaled register offset with update
265 InstrItinData<IIC_iLoad_siu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
266 InstrStage<1, [A9_MUX0], 0>,
267 InstrStage<1, [A9_AGU], 0>,
268 InstrStage<1, [A9_LSUnit]>],
269 [4, 3, 1, 1], [A9_LdBypass]>,
270 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
271 InstrStage<1, [A9_MUX0], 0>,
272 InstrStage<2, [A9_AGU], 0>,
273 InstrStage<1, [A9_LSUnit]>],
274 [5, 4, 1, 1], [A9_LdBypass]>,
276 // Load multiple, def is the 5th operand.
277 // FIXME: This assumes 3 to 4 registers.
278 InstrItinData<IIC_iLoad_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
279 InstrStage<1, [A9_MUX0], 0>,
280 InstrStage<2, [A9_AGU], 1>,
281 InstrStage<2, [A9_LSUnit]>],
283 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
285 // Load multiple + update, defs are the 1st and 5th operands.
286 InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
287 InstrStage<1, [A9_MUX0], 0>,
288 InstrStage<2, [A9_AGU], 1>,
289 InstrStage<2, [A9_LSUnit]>],
291 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
293 // Load multiple plus branch
294 InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
295 InstrStage<1, [A9_MUX0], 0>,
296 InstrStage<1, [A9_AGU], 1>,
297 InstrStage<2, [A9_LSUnit]>,
298 InstrStage<1, [A9_Branch]>],
300 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
302 // Pop, def is the 3rd operand.
303 InstrItinData<IIC_iPop , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
304 InstrStage<1, [A9_MUX0], 0>,
305 InstrStage<2, [A9_AGU], 1>,
306 InstrStage<2, [A9_LSUnit]>],
308 [NoBypass, NoBypass, A9_LdBypass]>,
310 // Pop + branch, def is the 3rd operand.
311 InstrItinData<IIC_iPop_Br, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
312 InstrStage<1, [A9_MUX0], 0>,
313 InstrStage<2, [A9_AGU], 1>,
314 InstrStage<2, [A9_LSUnit]>,
315 InstrStage<1, [A9_Branch]>],
317 [NoBypass, NoBypass, A9_LdBypass]>,
320 // iLoadi + iALUr for t2LDRpci_pic.
321 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
322 InstrStage<1, [A9_MUX0], 0>,
323 InstrStage<1, [A9_AGU], 0>,
324 InstrStage<1, [A9_LSUnit]>,
325 InstrStage<1, [A9_ALU0, A9_ALU1]>],
328 // Integer store pipeline
331 InstrItinData<IIC_iStore_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
332 InstrStage<1, [A9_MUX0], 0>,
333 InstrStage<1, [A9_AGU], 0>,
334 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
335 InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
336 InstrStage<1, [A9_MUX0], 0>,
337 InstrStage<2, [A9_AGU], 1>,
338 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
339 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
340 InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
341 InstrStage<1, [A9_MUX0], 0>,
342 InstrStage<2, [A9_AGU], 1>,
343 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
346 InstrItinData<IIC_iStore_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
347 InstrStage<1, [A9_MUX0], 0>,
348 InstrStage<1, [A9_AGU], 0>,
349 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
350 InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
351 InstrStage<1, [A9_MUX0], 0>,
352 InstrStage<2, [A9_AGU], 1>,
353 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
354 InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
355 InstrStage<1, [A9_MUX0], 0>,
356 InstrStage<2, [A9_AGU], 1>,
357 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
359 // Scaled register offset
360 InstrItinData<IIC_iStore_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
361 InstrStage<1, [A9_MUX0], 0>,
362 InstrStage<1, [A9_AGU], 0>,
363 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
364 InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
365 InstrStage<1, [A9_MUX0], 0>,
366 InstrStage<2, [A9_AGU], 1>,
367 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
369 // Immediate offset with update
370 InstrItinData<IIC_iStore_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
371 InstrStage<1, [A9_MUX0], 0>,
372 InstrStage<1, [A9_AGU], 0>,
373 InstrStage<1, [A9_LSUnit]>], [2, 1, 1]>,
374 InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
375 InstrStage<1, [A9_MUX0], 0>,
376 InstrStage<2, [A9_AGU], 1>,
377 InstrStage<1, [A9_LSUnit]>], [3, 1, 1]>,
379 // Register offset with update
380 InstrItinData<IIC_iStore_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
381 InstrStage<1, [A9_MUX0], 0>,
382 InstrStage<1, [A9_AGU], 0>,
383 InstrStage<1, [A9_LSUnit]>],
385 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
386 InstrStage<1, [A9_MUX0], 0>,
387 InstrStage<2, [A9_AGU], 1>,
388 InstrStage<1, [A9_LSUnit]>],
390 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
391 InstrStage<1, [A9_MUX0], 0>,
392 InstrStage<2, [A9_AGU], 1>,
393 InstrStage<1, [A9_LSUnit]>],
396 // Scaled register offset with update
397 InstrItinData<IIC_iStore_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
398 InstrStage<1, [A9_MUX0], 0>,
399 InstrStage<1, [A9_AGU], 0>,
400 InstrStage<1, [A9_LSUnit]>],
402 InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
403 InstrStage<1, [A9_MUX0], 0>,
404 InstrStage<2, [A9_AGU], 1>,
405 InstrStage<1, [A9_LSUnit]>],
409 InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
410 InstrStage<1, [A9_MUX0], 0>,
411 InstrStage<1, [A9_AGU], 0>,
412 InstrStage<2, [A9_LSUnit]>]>,
414 // Store multiple + update
415 InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
416 InstrStage<1, [A9_MUX0], 0>,
417 InstrStage<1, [A9_AGU], 0>,
418 InstrStage<2, [A9_LSUnit]>], [2]>,
422 InstrItinData<IIC_Preload, [InstrStage<1, [A9_Issue0, A9_Issue1]>], [1, 1]>,
426 // no delay slots, so the latency of a branch is unimportant
427 InstrItinData<IIC_Br , [InstrStage<1, [A9_Issue0], 0>,
428 InstrStage<1, [A9_Issue1], 0>,
429 InstrStage<1, [A9_Branch]>]>,
431 // VFP and NEON shares the same register file. This means that every VFP
432 // instruction should wait for full completion of the consecutive NEON
433 // instruction and vice-versa. We model this behavior with two artificial FUs:
434 // DRegsVFP and DRegsVFP.
436 // Every VFP instruction:
437 // - Acquires DRegsVFP resource for 1 cycle
438 // - Reserves DRegsN resource for the whole duration (including time to
439 // register file writeback!).
440 // Every NEON instruction does the same but with FUs swapped.
442 // Since the reserved FU cannot be acquired, this models precisely
443 // "cross-domain" stalls.
446 // Issue through integer pipeline, and execute in NEON unit.
448 // FP Special Register to Integer Register File Move
449 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
450 InstrStage<1, [A9_MUX0], 0>,
451 InstrStage<1, [A9_DRegsVFP], 0, Required>,
452 InstrStage<2, [A9_DRegsN], 0, Reserved>,
453 InstrStage<1, [A9_NPipe]>],
456 // Single-precision FP Unary
457 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
458 InstrStage<1, [A9_MUX0], 0>,
459 InstrStage<1, [A9_DRegsVFP], 0, Required>,
460 // Extra latency cycles since wbck is 2 cycles
461 InstrStage<3, [A9_DRegsN], 0, Reserved>,
462 InstrStage<1, [A9_NPipe]>],
465 // Double-precision FP Unary
466 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
467 InstrStage<1, [A9_MUX0], 0>,
468 InstrStage<1, [A9_DRegsVFP], 0, Required>,
469 // Extra latency cycles since wbck is 2 cycles
470 InstrStage<3, [A9_DRegsN], 0, Reserved>,
471 InstrStage<1, [A9_NPipe]>],
475 // Single-precision FP Compare
476 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
477 InstrStage<1, [A9_MUX0], 0>,
478 InstrStage<1, [A9_DRegsVFP], 0, Required>,
479 // Extra latency cycles since wbck is 4 cycles
480 InstrStage<5, [A9_DRegsN], 0, Reserved>,
481 InstrStage<1, [A9_NPipe]>],
484 // Double-precision FP Compare
485 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
486 InstrStage<1, [A9_MUX0], 0>,
487 InstrStage<1, [A9_DRegsVFP], 0, Required>,
488 // Extra latency cycles since wbck is 4 cycles
489 InstrStage<5, [A9_DRegsN], 0, Reserved>,
490 InstrStage<1, [A9_NPipe]>],
493 // Single to Double FP Convert
494 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
495 InstrStage<1, [A9_MUX0], 0>,
496 InstrStage<1, [A9_DRegsVFP], 0, Required>,
497 InstrStage<5, [A9_DRegsN], 0, Reserved>,
498 InstrStage<1, [A9_NPipe]>],
501 // Double to Single FP Convert
502 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
503 InstrStage<1, [A9_MUX0], 0>,
504 InstrStage<1, [A9_DRegsVFP], 0, Required>,
505 InstrStage<5, [A9_DRegsN], 0, Reserved>,
506 InstrStage<1, [A9_NPipe]>],
510 // Single to Half FP Convert
511 InstrItinData<IIC_fpCVTSH , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
512 InstrStage<1, [A9_MUX0], 0>,
513 InstrStage<1, [A9_DRegsVFP], 0, Required>,
514 InstrStage<5, [A9_DRegsN], 0, Reserved>,
515 InstrStage<1, [A9_NPipe]>],
518 // Half to Single FP Convert
519 InstrItinData<IIC_fpCVTHS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
520 InstrStage<1, [A9_MUX0], 0>,
521 InstrStage<1, [A9_DRegsVFP], 0, Required>,
522 InstrStage<3, [A9_DRegsN], 0, Reserved>,
523 InstrStage<1, [A9_NPipe]>],
527 // Single-Precision FP to Integer Convert
528 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
529 InstrStage<1, [A9_MUX0], 0>,
530 InstrStage<1, [A9_DRegsVFP], 0, Required>,
531 InstrStage<5, [A9_DRegsN], 0, Reserved>,
532 InstrStage<1, [A9_NPipe]>],
535 // Double-Precision FP to Integer Convert
536 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
537 InstrStage<1, [A9_MUX0], 0>,
538 InstrStage<1, [A9_DRegsVFP], 0, Required>,
539 InstrStage<5, [A9_DRegsN], 0, Reserved>,
540 InstrStage<1, [A9_NPipe]>],
543 // Integer to Single-Precision FP Convert
544 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
545 InstrStage<1, [A9_MUX0], 0>,
546 InstrStage<1, [A9_DRegsVFP], 0, Required>,
547 InstrStage<5, [A9_DRegsN], 0, Reserved>,
548 InstrStage<1, [A9_NPipe]>],
551 // Integer to Double-Precision FP Convert
552 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
553 InstrStage<1, [A9_MUX0], 0>,
554 InstrStage<1, [A9_DRegsVFP], 0, Required>,
555 InstrStage<5, [A9_DRegsN], 0, Reserved>,
556 InstrStage<1, [A9_NPipe]>],
559 // Single-precision FP ALU
560 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
561 InstrStage<1, [A9_MUX0], 0>,
562 InstrStage<1, [A9_DRegsVFP], 0, Required>,
563 InstrStage<5, [A9_DRegsN], 0, Reserved>,
564 InstrStage<1, [A9_NPipe]>],
567 // Double-precision FP ALU
568 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
569 InstrStage<1, [A9_MUX0], 0>,
570 InstrStage<1, [A9_DRegsVFP], 0, Required>,
571 InstrStage<5, [A9_DRegsN], 0, Reserved>,
572 InstrStage<1, [A9_NPipe]>],
575 // Single-precision FP Multiply
576 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
577 InstrStage<1, [A9_MUX0], 0>,
578 InstrStage<1, [A9_DRegsVFP], 0, Required>,
579 InstrStage<6, [A9_DRegsN], 0, Reserved>,
580 InstrStage<1, [A9_NPipe]>],
583 // Double-precision FP Multiply
584 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
585 InstrStage<1, [A9_MUX0], 0>,
586 InstrStage<1, [A9_DRegsVFP], 0, Required>,
587 InstrStage<7, [A9_DRegsN], 0, Reserved>,
588 InstrStage<2, [A9_NPipe]>],
591 // Single-precision FP MAC
592 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
593 InstrStage<1, [A9_MUX0], 0>,
594 InstrStage<1, [A9_DRegsVFP], 0, Required>,
595 InstrStage<9, [A9_DRegsN], 0, Reserved>,
596 InstrStage<1, [A9_NPipe]>],
599 // Double-precision FP MAC
600 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
601 InstrStage<1, [A9_MUX0], 0>,
602 InstrStage<1, [A9_DRegsVFP], 0, Required>,
603 InstrStage<10, [A9_DRegsN], 0, Reserved>,
604 InstrStage<2, [A9_NPipe]>],
607 // Single-precision FP DIV
608 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
609 InstrStage<1, [A9_MUX0], 0>,
610 InstrStage<1, [A9_DRegsVFP], 0, Required>,
611 InstrStage<16, [A9_DRegsN], 0, Reserved>,
612 InstrStage<10, [A9_NPipe]>],
615 // Double-precision FP DIV
616 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
617 InstrStage<1, [A9_MUX0], 0>,
618 InstrStage<1, [A9_DRegsVFP], 0, Required>,
619 InstrStage<26, [A9_DRegsN], 0, Reserved>,
620 InstrStage<20, [A9_NPipe]>],
623 // Single-precision FP SQRT
624 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
625 InstrStage<1, [A9_MUX0], 0>,
626 InstrStage<1, [A9_DRegsVFP], 0, Required>,
627 InstrStage<18, [A9_DRegsN], 0, Reserved>,
628 InstrStage<13, [A9_NPipe]>],
631 // Double-precision FP SQRT
632 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
633 InstrStage<1, [A9_MUX0], 0>,
634 InstrStage<1, [A9_DRegsVFP], 0, Required>,
635 InstrStage<33, [A9_DRegsN], 0, Reserved>,
636 InstrStage<28, [A9_NPipe]>],
640 // Integer to Single-precision Move
641 InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
642 InstrStage<1, [A9_MUX0], 0>,
643 InstrStage<1, [A9_DRegsVFP], 0, Required>,
644 // Extra 1 latency cycle since wbck is 2 cycles
645 InstrStage<3, [A9_DRegsN], 0, Reserved>,
646 InstrStage<1, [A9_NPipe]>],
649 // Integer to Double-precision Move
650 InstrItinData<IIC_fpMOVID, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
651 InstrStage<1, [A9_MUX0], 0>,
652 InstrStage<1, [A9_DRegsVFP], 0, Required>,
653 // Extra 1 latency cycle since wbck is 2 cycles
654 InstrStage<3, [A9_DRegsN], 0, Reserved>,
655 InstrStage<1, [A9_NPipe]>],
658 // Single-precision to Integer Move
659 InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
660 InstrStage<1, [A9_MUX0], 0>,
661 InstrStage<1, [A9_DRegsVFP], 0, Required>,
662 InstrStage<2, [A9_DRegsN], 0, Reserved>,
663 InstrStage<1, [A9_NPipe]>],
666 // Double-precision to Integer Move
667 InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
668 InstrStage<1, [A9_MUX0], 0>,
669 InstrStage<1, [A9_DRegsVFP], 0, Required>,
670 InstrStage<2, [A9_DRegsN], 0, Reserved>,
671 InstrStage<1, [A9_NPipe]>],
674 // Single-precision FP Load
675 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
676 InstrStage<1, [A9_MUX0], 0>,
677 InstrStage<1, [A9_DRegsVFP], 0, Required>,
678 InstrStage<2, [A9_DRegsN], 0, Reserved>,
679 InstrStage<1, [A9_NPipe], 0>,
680 InstrStage<1, [A9_LSUnit]>],
683 // Double-precision FP Load
684 // FIXME: Result latency is 1 if address is 64-bit aligned.
685 InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
686 InstrStage<1, [A9_MUX0], 0>,
687 InstrStage<1, [A9_DRegsVFP], 0, Required>,
688 InstrStage<2, [A9_DRegsN], 0, Reserved>,
689 InstrStage<1, [A9_NPipe], 0>,
690 InstrStage<1, [A9_LSUnit]>],
694 InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
695 InstrStage<1, [A9_MUX0], 0>,
696 InstrStage<1, [A9_DRegsVFP], 0, Required>,
697 InstrStage<2, [A9_DRegsN], 0, Reserved>,
698 InstrStage<1, [A9_NPipe], 0>,
699 InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>,
701 // FP Load Multiple + update
702 InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
703 InstrStage<1, [A9_MUX0], 0>,
704 InstrStage<1, [A9_DRegsVFP], 0, Required>,
705 InstrStage<2, [A9_DRegsN], 0, Reserved>,
706 InstrStage<1, [A9_NPipe], 0>,
707 InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>,
709 // Single-precision FP Store
710 InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
711 InstrStage<1, [A9_MUX0], 0>,
712 InstrStage<1, [A9_DRegsVFP], 0, Required>,
713 InstrStage<2, [A9_DRegsN], 0, Reserved>,
714 InstrStage<1, [A9_NPipe], 0>,
715 InstrStage<1, [A9_LSUnit]>],
718 // Double-precision FP Store
719 InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
720 InstrStage<1, [A9_MUX0], 0>,
721 InstrStage<1, [A9_DRegsVFP], 0, Required>,
722 InstrStage<2, [A9_DRegsN], 0, Reserved>,
723 InstrStage<1, [A9_NPipe], 0>,
724 InstrStage<1, [A9_LSUnit]>],
728 InstrItinData<IIC_fpStore_m,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
729 InstrStage<1, [A9_MUX0], 0>,
730 InstrStage<1, [A9_DRegsVFP], 0, Required>,
731 InstrStage<2, [A9_DRegsN], 0, Reserved>,
732 InstrStage<1, [A9_NPipe], 0>,
733 InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>,
735 // FP Store Multiple + update
736 InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
737 InstrStage<1, [A9_MUX0], 0>,
738 InstrStage<1, [A9_DRegsVFP], 0, Required>,
739 InstrStage<2, [A9_DRegsN], 0, Reserved>,
740 InstrStage<1, [A9_NPipe], 0>,
741 InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>,
744 // FIXME: Conservatively assume insufficent alignment.
745 InstrItinData<IIC_VLD1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
746 InstrStage<1, [A9_MUX0], 0>,
747 InstrStage<1, [A9_DRegsN], 0, Required>,
748 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
749 InstrStage<2, [A9_NPipe], 0>,
750 InstrStage<2, [A9_LSUnit]>],
753 InstrItinData<IIC_VLD1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
754 InstrStage<1, [A9_MUX0], 0>,
755 InstrStage<1, [A9_DRegsN], 0, Required>,
756 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
757 InstrStage<2, [A9_NPipe], 0>,
758 InstrStage<2, [A9_LSUnit]>],
761 InstrItinData<IIC_VLD1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
762 InstrStage<1, [A9_MUX0], 0>,
763 InstrStage<1, [A9_DRegsN], 0, Required>,
764 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
765 InstrStage<3, [A9_NPipe], 0>,
766 InstrStage<3, [A9_LSUnit]>],
769 InstrItinData<IIC_VLD1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
770 InstrStage<1, [A9_MUX0], 0>,
771 InstrStage<1, [A9_DRegsN], 0, Required>,
772 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
773 InstrStage<3, [A9_NPipe], 0>,
774 InstrStage<3, [A9_LSUnit]>],
777 InstrItinData<IIC_VLD1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
778 InstrStage<1, [A9_MUX0], 0>,
779 InstrStage<1, [A9_DRegsN], 0, Required>,
780 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
781 InstrStage<2, [A9_NPipe], 0>,
782 InstrStage<2, [A9_LSUnit]>],
785 InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
786 InstrStage<1, [A9_MUX0], 0>,
787 InstrStage<1, [A9_DRegsN], 0, Required>,
788 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
789 InstrStage<2, [A9_NPipe], 0>,
790 InstrStage<2, [A9_LSUnit]>],
793 InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
794 InstrStage<1, [A9_MUX0], 0>,
795 InstrStage<1, [A9_DRegsN], 0, Required>,
796 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
797 InstrStage<3, [A9_NPipe], 0>,
798 InstrStage<3, [A9_LSUnit]>],
801 InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
802 InstrStage<1, [A9_MUX0], 0>,
803 InstrStage<1, [A9_DRegsN], 0, Required>,
804 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
805 InstrStage<3, [A9_NPipe], 0>,
806 InstrStage<3, [A9_LSUnit]>],
810 InstrItinData<IIC_VLD1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
811 InstrStage<1, [A9_MUX0], 0>,
812 InstrStage<1, [A9_DRegsN], 0, Required>,
813 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
814 InstrStage<3, [A9_NPipe], 0>,
815 InstrStage<3, [A9_LSUnit]>],
819 InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
820 InstrStage<1, [A9_MUX0], 0>,
821 InstrStage<1, [A9_DRegsN], 0, Required>,
822 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
823 InstrStage<3, [A9_NPipe], 0>,
824 InstrStage<3, [A9_LSUnit]>],
828 InstrItinData<IIC_VLD1dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
829 InstrStage<1, [A9_MUX0], 0>,
830 InstrStage<1, [A9_DRegsN], 0, Required>,
831 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
832 InstrStage<2, [A9_NPipe], 0>,
833 InstrStage<2, [A9_LSUnit]>],
837 InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
838 InstrStage<1, [A9_MUX0], 0>,
839 InstrStage<1, [A9_DRegsN], 0, Required>,
840 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
841 InstrStage<2, [A9_NPipe], 0>,
842 InstrStage<2, [A9_LSUnit]>],
846 InstrItinData<IIC_VLD2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
847 InstrStage<1, [A9_MUX0], 0>,
848 InstrStage<1, [A9_DRegsN], 0, Required>,
849 // Extra latency cycles since wbck is 7 cycles
850 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
851 InstrStage<2, [A9_NPipe], 0>,
852 InstrStage<2, [A9_LSUnit]>],
856 InstrItinData<IIC_VLD2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
857 InstrStage<1, [A9_MUX0], 0>,
858 InstrStage<1, [A9_DRegsN], 0, Required>,
859 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
860 InstrStage<3, [A9_NPipe], 0>,
861 InstrStage<3, [A9_LSUnit]>],
865 InstrItinData<IIC_VLD2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
866 InstrStage<1, [A9_MUX0], 0>,
867 InstrStage<1, [A9_DRegsN], 0, Required>,
868 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
869 InstrStage<3, [A9_NPipe], 0>,
870 InstrStage<3, [A9_LSUnit]>],
874 InstrItinData<IIC_VLD2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
875 InstrStage<1, [A9_MUX0], 0>,
876 InstrStage<1, [A9_DRegsN], 0, Required>,
877 // Extra latency cycles since wbck is 7 cycles
878 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
879 InstrStage<2, [A9_NPipe], 0>,
880 InstrStage<2, [A9_LSUnit]>],
884 InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
885 InstrStage<1, [A9_MUX0], 0>,
886 InstrStage<1, [A9_DRegsN], 0, Required>,
887 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
888 InstrStage<3, [A9_NPipe], 0>,
889 InstrStage<3, [A9_LSUnit]>],
893 InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
894 InstrStage<1, [A9_MUX0], 0>,
895 InstrStage<1, [A9_DRegsN], 0, Required>,
896 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
897 InstrStage<3, [A9_NPipe], 0>,
898 InstrStage<3, [A9_LSUnit]>],
899 [4, 4, 2, 1, 1, 1, 1, 1]>,
902 InstrItinData<IIC_VLD2dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
903 InstrStage<1, [A9_MUX0], 0>,
904 InstrStage<1, [A9_DRegsN], 0, Required>,
905 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
906 InstrStage<2, [A9_NPipe], 0>,
907 InstrStage<2, [A9_LSUnit]>],
911 InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
912 InstrStage<1, [A9_MUX0], 0>,
913 InstrStage<1, [A9_DRegsN], 0, Required>,
914 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
915 InstrStage<2, [A9_NPipe], 0>,
916 InstrStage<2, [A9_LSUnit]>],
920 InstrItinData<IIC_VLD3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
921 InstrStage<1, [A9_MUX0], 0>,
922 InstrStage<1, [A9_DRegsN], 0, Required>,
923 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
924 InstrStage<4, [A9_NPipe], 0>,
925 InstrStage<4, [A9_LSUnit]>],
929 InstrItinData<IIC_VLD3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
930 InstrStage<1, [A9_MUX0], 0>,
931 InstrStage<1, [A9_DRegsN], 0, Required>,
932 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
933 InstrStage<5, [A9_NPipe], 0>,
934 InstrStage<5, [A9_LSUnit]>],
935 [5, 5, 6, 1, 1, 1, 1, 2]>,
938 InstrItinData<IIC_VLD3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
939 InstrStage<1, [A9_MUX0], 0>,
940 InstrStage<1, [A9_DRegsN], 0, Required>,
941 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
942 InstrStage<4, [A9_NPipe], 0>,
943 InstrStage<4, [A9_LSUnit]>],
947 InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
948 InstrStage<1, [A9_MUX0], 0>,
949 InstrStage<1, [A9_DRegsN], 0, Required>,
950 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
951 InstrStage<5, [A9_NPipe], 0>,
952 InstrStage<5, [A9_LSUnit]>],
953 [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>,
956 InstrItinData<IIC_VLD3dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
957 InstrStage<1, [A9_MUX0], 0>,
958 InstrStage<1, [A9_DRegsN], 0, Required>,
959 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
960 InstrStage<3, [A9_NPipe], 0>,
961 InstrStage<3, [A9_LSUnit]>],
965 InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
966 InstrStage<1, [A9_MUX0], 0>,
967 InstrStage<1, [A9_DRegsN], 0, Required>,
968 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
969 InstrStage<3, [A9_NPipe], 0>,
970 InstrStage<3, [A9_LSUnit]>],
974 InstrItinData<IIC_VLD4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
975 InstrStage<1, [A9_MUX0], 0>,
976 InstrStage<1, [A9_DRegsN], 0, Required>,
977 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
978 InstrStage<4, [A9_NPipe], 0>,
979 InstrStage<4, [A9_LSUnit]>],
983 InstrItinData<IIC_VLD4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
984 InstrStage<1, [A9_MUX0], 0>,
985 InstrStage<1, [A9_DRegsN], 0, Required>,
986 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
987 InstrStage<5, [A9_NPipe], 0>,
988 InstrStage<5, [A9_LSUnit]>],
989 [5, 5, 6, 6, 1, 1, 1, 1, 2, 2]>,
992 InstrItinData<IIC_VLD4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
993 InstrStage<1, [A9_MUX0], 0>,
994 InstrStage<1, [A9_DRegsN], 0, Required>,
995 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
996 InstrStage<4, [A9_NPipe], 0>,
997 InstrStage<4, [A9_LSUnit]>],
1001 InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1002 InstrStage<1, [A9_MUX0], 0>,
1003 InstrStage<1, [A9_DRegsN], 0, Required>,
1004 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
1005 InstrStage<5, [A9_NPipe], 0>,
1006 InstrStage<5, [A9_LSUnit]>],
1007 [5, 5, 6, 6, 2, 1, 1, 1, 1, 1, 2, 2]>,
1010 InstrItinData<IIC_VLD4dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1011 InstrStage<1, [A9_MUX0], 0>,
1012 InstrStage<1, [A9_DRegsN], 0, Required>,
1013 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1014 InstrStage<3, [A9_NPipe], 0>,
1015 InstrStage<3, [A9_LSUnit]>],
1019 InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1020 InstrStage<1, [A9_MUX0], 0>,
1021 InstrStage<1, [A9_DRegsN], 0, Required>,
1022 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1023 InstrStage<3, [A9_NPipe], 0>,
1024 InstrStage<3, [A9_LSUnit]>],
1025 [3, 3, 4, 4, 2, 1, 1]>,
1028 InstrItinData<IIC_VST1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1029 InstrStage<1, [A9_MUX0], 0>,
1030 InstrStage<1, [A9_DRegsN], 0, Required>,
1031 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1032 InstrStage<2, [A9_NPipe], 0>,
1033 InstrStage<2, [A9_LSUnit]>],
1037 InstrItinData<IIC_VST1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1038 InstrStage<1, [A9_MUX0], 0>,
1039 InstrStage<1, [A9_DRegsN], 0, Required>,
1040 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1041 InstrStage<2, [A9_NPipe], 0>,
1042 InstrStage<2, [A9_LSUnit]>],
1046 InstrItinData<IIC_VST1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1047 InstrStage<1, [A9_MUX0], 0>,
1048 InstrStage<1, [A9_DRegsN], 0, Required>,
1049 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1050 InstrStage<3, [A9_NPipe], 0>,
1051 InstrStage<3, [A9_LSUnit]>],
1055 InstrItinData<IIC_VST1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1056 InstrStage<1, [A9_MUX0], 0>,
1057 InstrStage<1, [A9_DRegsN], 0, Required>,
1058 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1059 InstrStage<3, [A9_NPipe], 0>,
1060 InstrStage<3, [A9_LSUnit]>],
1061 [1, 1, 1, 1, 2, 2]>,
1064 InstrItinData<IIC_VST1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1065 InstrStage<1, [A9_MUX0], 0>,
1066 InstrStage<1, [A9_DRegsN], 0, Required>,
1067 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1068 InstrStage<2, [A9_NPipe], 0>,
1069 InstrStage<2, [A9_LSUnit]>],
1073 InstrItinData<IIC_VST1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1074 InstrStage<1, [A9_MUX0], 0>,
1075 InstrStage<1, [A9_DRegsN], 0, Required>,
1076 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1077 InstrStage<2, [A9_NPipe], 0>,
1078 InstrStage<2, [A9_LSUnit]>],
1079 [2, 1, 1, 1, 1, 1]>,
1082 InstrItinData<IIC_VST1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1083 InstrStage<1, [A9_MUX0], 0>,
1084 InstrStage<1, [A9_DRegsN], 0, Required>,
1085 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1086 InstrStage<3, [A9_NPipe], 0>,
1087 InstrStage<3, [A9_LSUnit]>],
1088 [2, 1, 1, 1, 1, 1, 2]>,
1091 InstrItinData<IIC_VST1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1092 InstrStage<1, [A9_MUX0], 0>,
1093 InstrStage<1, [A9_DRegsN], 0, Required>,
1094 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1095 InstrStage<3, [A9_NPipe], 0>,
1096 InstrStage<3, [A9_LSUnit]>],
1097 [2, 1, 1, 1, 1, 1, 2, 2]>,
1100 InstrItinData<IIC_VST1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1101 InstrStage<1, [A9_MUX0], 0>,
1102 InstrStage<1, [A9_DRegsN], 0, Required>,
1103 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1104 InstrStage<2, [A9_NPipe], 0>,
1105 InstrStage<2, [A9_LSUnit]>],
1109 InstrItinData<IIC_VST1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1110 InstrStage<1, [A9_MUX0], 0>,
1111 InstrStage<1, [A9_DRegsN], 0, Required>,
1112 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1113 InstrStage<3, [A9_NPipe], 0>,
1114 InstrStage<3, [A9_LSUnit]>],
1118 InstrItinData<IIC_VST2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1119 InstrStage<1, [A9_MUX0], 0>,
1120 InstrStage<1, [A9_DRegsN], 0, Required>,
1121 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1122 InstrStage<2, [A9_NPipe], 0>,
1123 InstrStage<2, [A9_LSUnit]>],
1127 InstrItinData<IIC_VST2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1128 InstrStage<1, [A9_MUX0], 0>,
1129 InstrStage<1, [A9_DRegsN], 0, Required>,
1130 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1131 InstrStage<3, [A9_NPipe], 0>,
1132 InstrStage<3, [A9_LSUnit]>],
1133 [1, 1, 1, 1, 2, 2]>,
1136 InstrItinData<IIC_VST2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1137 InstrStage<1, [A9_MUX0], 0>,
1138 InstrStage<1, [A9_DRegsN], 0, Required>,
1139 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1140 InstrStage<2, [A9_NPipe], 0>,
1141 InstrStage<2, [A9_LSUnit]>],
1142 [2, 1, 1, 1, 1, 1]>,
1145 InstrItinData<IIC_VST2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1146 InstrStage<1, [A9_MUX0], 0>,
1147 InstrStage<1, [A9_DRegsN], 0, Required>,
1148 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1149 InstrStage<3, [A9_NPipe], 0>,
1150 InstrStage<3, [A9_LSUnit]>],
1151 [2, 1, 1, 1, 1, 1, 2, 2]>,
1154 InstrItinData<IIC_VST2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1155 InstrStage<1, [A9_MUX0], 0>,
1156 InstrStage<1, [A9_DRegsN], 0, Required>,
1157 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1158 InstrStage<2, [A9_NPipe], 0>,
1159 InstrStage<2, [A9_LSUnit]>],
1163 InstrItinData<IIC_VST2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1164 InstrStage<1, [A9_MUX0], 0>,
1165 InstrStage<1, [A9_DRegsN], 0, Required>,
1166 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1167 InstrStage<3, [A9_NPipe], 0>,
1168 InstrStage<3, [A9_LSUnit]>],
1169 [2, 1, 1, 1, 1, 1]>,
1172 InstrItinData<IIC_VST3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1173 InstrStage<1, [A9_MUX0], 0>,
1174 InstrStage<1, [A9_DRegsN], 0, Required>,
1175 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1176 InstrStage<3, [A9_NPipe], 0>,
1177 InstrStage<3, [A9_LSUnit]>],
1181 InstrItinData<IIC_VST3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1182 InstrStage<1, [A9_MUX0], 0>,
1183 InstrStage<1, [A9_DRegsN], 0, Required>,
1184 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1185 InstrStage<3, [A9_NPipe], 0>,
1186 InstrStage<3, [A9_LSUnit]>],
1187 [2, 1, 1, 1, 1, 1, 2]>,
1190 InstrItinData<IIC_VST3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1191 InstrStage<1, [A9_MUX0], 0>,
1192 InstrStage<1, [A9_DRegsN], 0, Required>,
1193 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1194 InstrStage<3, [A9_NPipe], 0>,
1195 InstrStage<3, [A9_LSUnit]>],
1199 InstrItinData<IIC_VST3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1200 InstrStage<1, [A9_MUX0], 0>,
1201 InstrStage<1, [A9_DRegsN], 0, Required>,
1202 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1203 InstrStage<3, [A9_NPipe], 0>,
1204 InstrStage<3, [A9_LSUnit]>],
1205 [2, 1, 1, 1, 1, 1, 2]>,
1208 InstrItinData<IIC_VST4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1209 InstrStage<1, [A9_MUX0], 0>,
1210 InstrStage<1, [A9_DRegsN], 0, Required>,
1211 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1212 InstrStage<3, [A9_NPipe], 0>,
1213 InstrStage<3, [A9_LSUnit]>],
1214 [1, 1, 1, 1, 2, 2]>,
1217 InstrItinData<IIC_VST4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1218 InstrStage<1, [A9_MUX0], 0>,
1219 InstrStage<1, [A9_DRegsN], 0, Required>,
1220 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1221 InstrStage<3, [A9_NPipe], 0>,
1222 InstrStage<3, [A9_LSUnit]>],
1223 [2, 1, 1, 1, 1, 1, 2, 2]>,
1226 InstrItinData<IIC_VST4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1227 InstrStage<1, [A9_MUX0], 0>,
1228 InstrStage<1, [A9_DRegsN], 0, Required>,
1229 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1230 InstrStage<3, [A9_NPipe], 0>,
1231 InstrStage<3, [A9_LSUnit]>],
1232 [1, 1, 1, 1, 2, 2]>,
1235 InstrItinData<IIC_VST4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1236 InstrStage<1, [A9_MUX0], 0>,
1237 InstrStage<1, [A9_DRegsN], 0, Required>,
1238 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1239 InstrStage<3, [A9_NPipe], 0>,
1240 InstrStage<3, [A9_LSUnit]>],
1241 [2, 1, 1, 1, 1, 1, 2, 2]>,
1244 // Double-register Integer Unary
1245 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1246 InstrStage<1, [A9_MUX0], 0>,
1247 InstrStage<1, [A9_DRegsN], 0, Required>,
1248 // Extra latency cycles since wbck is 6 cycles
1249 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1250 InstrStage<1, [A9_NPipe]>],
1253 // Quad-register Integer Unary
1254 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1255 InstrStage<1, [A9_MUX0], 0>,
1256 InstrStage<1, [A9_DRegsN], 0, Required>,
1257 // Extra latency cycles since wbck is 6 cycles
1258 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1259 InstrStage<1, [A9_NPipe]>],
1262 // Double-register Integer Q-Unary
1263 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1264 InstrStage<1, [A9_MUX0], 0>,
1265 InstrStage<1, [A9_DRegsN], 0, Required>,
1266 // Extra latency cycles since wbck is 6 cycles
1267 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1268 InstrStage<1, [A9_NPipe]>],
1271 // Quad-register Integer CountQ-Unary
1272 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1273 InstrStage<1, [A9_MUX0], 0>,
1274 InstrStage<1, [A9_DRegsN], 0, Required>,
1275 // Extra latency cycles since wbck is 6 cycles
1276 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1277 InstrStage<1, [A9_NPipe]>],
1280 // Double-register Integer Binary
1281 InstrItinData<IIC_VBINiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1282 InstrStage<1, [A9_MUX0], 0>,
1283 InstrStage<1, [A9_DRegsN], 0, Required>,
1284 // Extra latency cycles since wbck is 6 cycles
1285 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1286 InstrStage<1, [A9_NPipe]>],
1289 // Quad-register Integer Binary
1290 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1291 InstrStage<1, [A9_MUX0], 0>,
1292 InstrStage<1, [A9_DRegsN], 0, Required>,
1293 // Extra latency cycles since wbck is 6 cycles
1294 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1295 InstrStage<1, [A9_NPipe]>],
1298 // Double-register Integer Subtract
1299 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1300 InstrStage<1, [A9_MUX0], 0>,
1301 InstrStage<1, [A9_DRegsN], 0, Required>,
1302 // Extra latency cycles since wbck is 6 cycles
1303 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1304 InstrStage<1, [A9_NPipe]>],
1307 // Quad-register Integer Subtract
1308 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1309 InstrStage<1, [A9_MUX0], 0>,
1310 InstrStage<1, [A9_DRegsN], 0, Required>,
1311 // Extra latency cycles since wbck is 6 cycles
1312 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1313 InstrStage<1, [A9_NPipe]>],
1316 // Double-register Integer Shift
1317 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1318 InstrStage<1, [A9_MUX0], 0>,
1319 InstrStage<1, [A9_DRegsN], 0, Required>,
1320 // Extra latency cycles since wbck is 6 cycles
1321 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1322 InstrStage<1, [A9_NPipe]>],
1325 // Quad-register Integer Shift
1326 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1327 InstrStage<1, [A9_MUX0], 0>,
1328 InstrStage<1, [A9_DRegsN], 0, Required>,
1329 // Extra latency cycles since wbck is 6 cycles
1330 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1331 InstrStage<1, [A9_NPipe]>],
1334 // Double-register Integer Shift (4 cycle)
1335 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1336 InstrStage<1, [A9_MUX0], 0>,
1337 InstrStage<1, [A9_DRegsN], 0, Required>,
1338 // Extra latency cycles since wbck is 6 cycles
1339 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1340 InstrStage<1, [A9_NPipe]>],
1343 // Quad-register Integer Shift (4 cycle)
1344 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1345 InstrStage<1, [A9_MUX0], 0>,
1346 InstrStage<1, [A9_DRegsN], 0, Required>,
1347 // Extra latency cycles since wbck is 6 cycles
1348 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1349 InstrStage<1, [A9_NPipe]>],
1352 // Double-register Integer Binary (4 cycle)
1353 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1354 InstrStage<1, [A9_MUX0], 0>,
1355 InstrStage<1, [A9_DRegsN], 0, Required>,
1356 // Extra latency cycles since wbck is 6 cycles
1357 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1358 InstrStage<1, [A9_NPipe]>],
1361 // Quad-register Integer Binary (4 cycle)
1362 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1363 InstrStage<1, [A9_MUX0], 0>,
1364 InstrStage<1, [A9_DRegsN], 0, Required>,
1365 // Extra latency cycles since wbck is 6 cycles
1366 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1367 InstrStage<1, [A9_NPipe]>],
1370 // Double-register Integer Subtract (4 cycle)
1371 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1372 InstrStage<1, [A9_MUX0], 0>,
1373 InstrStage<1, [A9_DRegsN], 0, Required>,
1374 // Extra latency cycles since wbck is 6 cycles
1375 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1376 InstrStage<1, [A9_NPipe]>],
1379 // Quad-register Integer Subtract (4 cycle)
1380 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1381 InstrStage<1, [A9_MUX0], 0>,
1382 InstrStage<1, [A9_DRegsN], 0, Required>,
1383 // Extra latency cycles since wbck is 6 cycles
1384 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1385 InstrStage<1, [A9_NPipe]>],
1389 // Double-register Integer Count
1390 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1391 InstrStage<1, [A9_MUX0], 0>,
1392 InstrStage<1, [A9_DRegsN], 0, Required>,
1393 // Extra latency cycles since wbck is 6 cycles
1394 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1395 InstrStage<1, [A9_NPipe]>],
1398 // Quad-register Integer Count
1399 // Result written in N3, but that is relative to the last cycle of multicycle,
1400 // so we use 4 for those cases
1401 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1402 InstrStage<1, [A9_MUX0], 0>,
1403 InstrStage<1, [A9_DRegsN], 0, Required>,
1404 // Extra latency cycles since wbck is 7 cycles
1405 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1406 InstrStage<2, [A9_NPipe]>],
1409 // Double-register Absolute Difference and Accumulate
1410 InstrItinData<IIC_VABAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1411 InstrStage<1, [A9_MUX0], 0>,
1412 InstrStage<1, [A9_DRegsN], 0, Required>,
1413 // Extra latency cycles since wbck is 6 cycles
1414 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1415 InstrStage<1, [A9_NPipe]>],
1418 // Quad-register Absolute Difference and Accumulate
1419 InstrItinData<IIC_VABAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1420 InstrStage<1, [A9_MUX0], 0>,
1421 InstrStage<1, [A9_DRegsN], 0, Required>,
1422 // Extra latency cycles since wbck is 6 cycles
1423 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1424 InstrStage<2, [A9_NPipe]>],
1427 // Double-register Integer Pair Add Long
1428 InstrItinData<IIC_VPALiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1429 InstrStage<1, [A9_MUX0], 0>,
1430 InstrStage<1, [A9_DRegsN], 0, Required>,
1431 // Extra latency cycles since wbck is 6 cycles
1432 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1433 InstrStage<1, [A9_NPipe]>],
1436 // Quad-register Integer Pair Add Long
1437 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1438 InstrStage<1, [A9_MUX0], 0>,
1439 InstrStage<1, [A9_DRegsN], 0, Required>,
1440 // Extra latency cycles since wbck is 6 cycles
1441 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1442 InstrStage<2, [A9_NPipe]>],
1446 // Double-register Integer Multiply (.8, .16)
1447 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1448 InstrStage<1, [A9_MUX0], 0>,
1449 InstrStage<1, [A9_DRegsN], 0, Required>,
1450 // Extra latency cycles since wbck is 6 cycles
1451 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1452 InstrStage<1, [A9_NPipe]>],
1455 // Quad-register Integer Multiply (.8, .16)
1456 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1457 InstrStage<1, [A9_MUX0], 0>,
1458 InstrStage<1, [A9_DRegsN], 0, Required>,
1459 // Extra latency cycles since wbck is 7 cycles
1460 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1461 InstrStage<2, [A9_NPipe]>],
1465 // Double-register Integer Multiply (.32)
1466 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1467 InstrStage<1, [A9_MUX0], 0>,
1468 InstrStage<1, [A9_DRegsN], 0, Required>,
1469 // Extra latency cycles since wbck is 7 cycles
1470 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1471 InstrStage<2, [A9_NPipe]>],
1474 // Quad-register Integer Multiply (.32)
1475 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1476 InstrStage<1, [A9_MUX0], 0>,
1477 InstrStage<1, [A9_DRegsN], 0, Required>,
1478 // Extra latency cycles since wbck is 9 cycles
1479 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
1480 InstrStage<4, [A9_NPipe]>],
1483 // Double-register Integer Multiply-Accumulate (.8, .16)
1484 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1485 InstrStage<1, [A9_MUX0], 0>,
1486 InstrStage<1, [A9_DRegsN], 0, Required>,
1487 // Extra latency cycles since wbck is 6 cycles
1488 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1489 InstrStage<1, [A9_NPipe]>],
1492 // Double-register Integer Multiply-Accumulate (.32)
1493 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1494 InstrStage<1, [A9_MUX0], 0>,
1495 InstrStage<1, [A9_DRegsN], 0, Required>,
1496 // Extra latency cycles since wbck is 7 cycles
1497 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1498 InstrStage<2, [A9_NPipe]>],
1501 // Quad-register Integer Multiply-Accumulate (.8, .16)
1502 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1503 InstrStage<1, [A9_MUX0], 0>,
1504 InstrStage<1, [A9_DRegsN], 0, Required>,
1505 // Extra latency cycles since wbck is 7 cycles
1506 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1507 InstrStage<2, [A9_NPipe]>],
1510 // Quad-register Integer Multiply-Accumulate (.32)
1511 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1512 InstrStage<1, [A9_MUX0], 0>,
1513 InstrStage<1, [A9_DRegsN], 0, Required>,
1514 // Extra latency cycles since wbck is 9 cycles
1515 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
1516 InstrStage<4, [A9_NPipe]>],
1521 InstrItinData<IIC_VMOV, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1522 InstrStage<1, [A9_MUX0], 0>,
1523 InstrStage<1, [A9_DRegsN], 0, Required>,
1524 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1525 InstrStage<1, [A9_NPipe]>],
1529 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1530 InstrStage<1, [A9_MUX0], 0>,
1531 InstrStage<1, [A9_DRegsN], 0, Required>,
1532 // Extra latency cycles since wbck is 6 cycles
1533 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1534 InstrStage<1, [A9_NPipe]>],
1537 // Double-register Permute Move
1538 InstrItinData<IIC_VMOVD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1539 InstrStage<1, [A9_MUX0], 0>,
1540 InstrStage<1, [A9_DRegsN], 0, Required>,
1541 // Extra latency cycles since wbck is 6 cycles
1542 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1543 InstrStage<1, [A9_NPipe]>],
1546 // Quad-register Permute Move
1547 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1548 InstrStage<1, [A9_MUX0], 0>,
1549 InstrStage<1, [A9_DRegsN], 0, Required>,
1550 // Extra latency cycles since wbck is 6 cycles
1551 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1552 InstrStage<1, [A9_NPipe]>],
1555 // Integer to Single-precision Move
1556 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1557 InstrStage<1, [A9_MUX0], 0>,
1558 InstrStage<1, [A9_DRegsN], 0, Required>,
1559 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1560 InstrStage<1, [A9_NPipe]>],
1563 // Integer to Double-precision Move
1564 InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1565 InstrStage<1, [A9_MUX0], 0>,
1566 InstrStage<1, [A9_DRegsN], 0, Required>,
1567 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1568 InstrStage<1, [A9_NPipe]>],
1571 // Single-precision to Integer Move
1572 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1573 InstrStage<1, [A9_MUX0], 0>,
1574 InstrStage<1, [A9_DRegsN], 0, Required>,
1575 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1576 InstrStage<1, [A9_NPipe]>],
1579 // Double-precision to Integer Move
1580 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1581 InstrStage<1, [A9_MUX0], 0>,
1582 InstrStage<1, [A9_DRegsN], 0, Required>,
1583 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1584 InstrStage<1, [A9_NPipe]>],
1587 // Integer to Lane Move
1588 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1589 InstrStage<1, [A9_MUX0], 0>,
1590 InstrStage<1, [A9_DRegsN], 0, Required>,
1591 InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
1592 InstrStage<2, [A9_NPipe]>],
1596 // Vector narrow move
1597 InstrItinData<IIC_VMOVN, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1598 InstrStage<1, [A9_MUX0], 0>,
1599 InstrStage<1, [A9_DRegsN], 0, Required>,
1600 // Extra latency cycles since wbck is 6 cycles
1601 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1602 InstrStage<1, [A9_NPipe]>],
1605 // Double-register FP Unary
1606 InstrItinData<IIC_VUNAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1607 InstrStage<1, [A9_MUX0], 0>,
1608 InstrStage<1, [A9_DRegsN], 0, Required>,
1609 // Extra latency cycles since wbck is 6 cycles
1610 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1611 InstrStage<1, [A9_NPipe]>],
1614 // Quad-register FP Unary
1615 // Result written in N5, but that is relative to the last cycle of multicycle,
1616 // so we use 6 for those cases
1617 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1618 InstrStage<1, [A9_MUX0], 0>,
1619 InstrStage<1, [A9_DRegsN], 0, Required>,
1620 // Extra latency cycles since wbck is 7 cycles
1621 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1622 InstrStage<2, [A9_NPipe]>],
1625 // Double-register FP Binary
1626 // FIXME: We're using this itin for many instructions and [2, 2] here is too
1628 InstrItinData<IIC_VBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1629 InstrStage<1, [A9_MUX0], 0>,
1630 InstrStage<1, [A9_DRegsN], 0, Required>,
1631 // Extra latency cycles since wbck is 6 cycles
1632 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1633 InstrStage<1, [A9_NPipe]>],
1638 InstrItinData<IIC_VPBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1639 InstrStage<1, [A9_MUX0], 0>,
1640 InstrStage<1, [A9_DRegsN], 0, Required>,
1641 // Extra latency cycles since wbck is 6 cycles
1642 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1643 InstrStage<1, [A9_NPipe]>],
1646 // Double-register FP VMUL
1647 InstrItinData<IIC_VFMULD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1648 InstrStage<1, [A9_MUX0], 0>,
1649 InstrStage<1, [A9_DRegsN], 0, Required>,
1650 // Extra latency cycles since wbck is 6 cycles
1651 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1652 InstrStage<1, [A9_NPipe]>],
1655 // Quad-register FP Binary
1656 // Result written in N5, but that is relative to the last cycle of multicycle,
1657 // so we use 6 for those cases
1658 // FIXME: We're using this itin for many instructions and [2, 2] here is too
1660 InstrItinData<IIC_VBINQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1661 InstrStage<1, [A9_MUX0], 0>,
1662 InstrStage<1, [A9_DRegsN], 0, Required>,
1663 // Extra latency cycles since wbck is 7 cycles
1664 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1665 InstrStage<2, [A9_NPipe]>],
1668 // Quad-register FP VMUL
1669 InstrItinData<IIC_VFMULQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1670 InstrStage<1, [A9_MUX0], 0>,
1671 InstrStage<1, [A9_DRegsN], 0, Required>,
1672 // Extra latency cycles since wbck is 7 cycles
1673 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1674 InstrStage<1, [A9_NPipe]>],
1677 // Double-register FP Multiple-Accumulate
1678 InstrItinData<IIC_VMACD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1679 InstrStage<1, [A9_MUX0], 0>,
1680 InstrStage<1, [A9_DRegsN], 0, Required>,
1681 // Extra latency cycles since wbck is 7 cycles
1682 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1683 InstrStage<2, [A9_NPipe]>],
1686 // Quad-register FP Multiple-Accumulate
1687 // Result written in N9, but that is relative to the last cycle of multicycle,
1688 // so we use 10 for those cases
1689 InstrItinData<IIC_VMACQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1690 InstrStage<1, [A9_MUX0], 0>,
1691 InstrStage<1, [A9_DRegsN], 0, Required>,
1692 // Extra latency cycles since wbck is 9 cycles
1693 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
1694 InstrStage<4, [A9_NPipe]>],
1697 // Double-register Reciprical Step
1698 InstrItinData<IIC_VRECSD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1699 InstrStage<1, [A9_MUX0], 0>,
1700 InstrStage<1, [A9_DRegsN], 0, Required>,
1701 // Extra latency cycles since wbck is 10 cycles
1702 InstrStage<11, [A9_DRegsVFP], 0, Reserved>,
1703 InstrStage<1, [A9_NPipe]>],
1706 // Quad-register Reciprical Step
1707 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1708 InstrStage<1, [A9_MUX0], 0>,
1709 InstrStage<1, [A9_DRegsN], 0, Required>,
1710 // Extra latency cycles since wbck is 11 cycles
1711 InstrStage<12, [A9_DRegsVFP], 0, Reserved>,
1712 InstrStage<2, [A9_NPipe]>],
1715 // Double-register Permute
1716 InstrItinData<IIC_VPERMD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1717 InstrStage<1, [A9_MUX0], 0>,
1718 InstrStage<1, [A9_DRegsN], 0, Required>,
1719 // Extra latency cycles since wbck is 6 cycles
1720 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1721 InstrStage<1, [A9_NPipe]>],
1724 // Quad-register Permute
1725 // Result written in N2, but that is relative to the last cycle of multicycle,
1726 // so we use 3 for those cases
1727 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1728 InstrStage<1, [A9_MUX0], 0>,
1729 InstrStage<1, [A9_DRegsN], 0, Required>,
1730 // Extra latency cycles since wbck is 7 cycles
1731 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1732 InstrStage<2, [A9_NPipe]>],
1735 // Quad-register Permute (3 cycle issue)
1736 // Result written in N2, but that is relative to the last cycle of multicycle,
1737 // so we use 4 for those cases
1738 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1739 InstrStage<1, [A9_MUX0], 0>,
1740 InstrStage<1, [A9_DRegsN], 0, Required>,
1741 // Extra latency cycles since wbck is 8 cycles
1742 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1743 InstrStage<3, [A9_NPipe]>],
1747 // Double-register VEXT
1748 InstrItinData<IIC_VEXTD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1749 InstrStage<1, [A9_MUX0], 0>,
1750 InstrStage<1, [A9_DRegsN], 0, Required>,
1751 // Extra latency cycles since wbck is 6 cycles
1752 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1753 InstrStage<1, [A9_NPipe]>],
1756 // Quad-register VEXT
1757 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1758 InstrStage<1, [A9_MUX0], 0>,
1759 InstrStage<1, [A9_DRegsN], 0, Required>,
1760 // Extra latency cycles since wbck is 7 cycles
1761 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1762 InstrStage<2, [A9_NPipe]>],
1766 InstrItinData<IIC_VTB1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1767 InstrStage<1, [A9_MUX0], 0>,
1768 InstrStage<1, [A9_DRegsN], 0, Required>,
1769 // Extra latency cycles since wbck is 7 cycles
1770 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1771 InstrStage<2, [A9_NPipe]>],
1773 InstrItinData<IIC_VTB2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1774 InstrStage<1, [A9_MUX0], 0>,
1775 InstrStage<2, [A9_DRegsN], 0, Required>,
1776 // Extra latency cycles since wbck is 7 cycles
1777 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1778 InstrStage<2, [A9_NPipe]>],
1780 InstrItinData<IIC_VTB3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1781 InstrStage<1, [A9_MUX0], 0>,
1782 InstrStage<2, [A9_DRegsN], 0, Required>,
1783 // Extra latency cycles since wbck is 8 cycles
1784 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1785 InstrStage<3, [A9_NPipe]>],
1787 InstrItinData<IIC_VTB4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1788 InstrStage<1, [A9_MUX0], 0>,
1789 InstrStage<1, [A9_DRegsN], 0, Required>,
1790 // Extra latency cycles since wbck is 8 cycles
1791 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1792 InstrStage<3, [A9_NPipe]>],
1793 [4, 2, 2, 3, 3, 1]>,
1796 InstrItinData<IIC_VTBX1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1797 InstrStage<1, [A9_MUX0], 0>,
1798 InstrStage<1, [A9_DRegsN], 0, Required>,
1799 // Extra latency cycles since wbck is 7 cycles
1800 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1801 InstrStage<2, [A9_NPipe]>],
1803 InstrItinData<IIC_VTBX2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1804 InstrStage<1, [A9_MUX0], 0>,
1805 InstrStage<1, [A9_DRegsN], 0, Required>,
1806 // Extra latency cycles since wbck is 7 cycles
1807 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1808 InstrStage<2, [A9_NPipe]>],
1810 InstrItinData<IIC_VTBX3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1811 InstrStage<1, [A9_MUX0], 0>,
1812 InstrStage<1, [A9_DRegsN], 0, Required>,
1813 // Extra latency cycles since wbck is 8 cycles
1814 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1815 InstrStage<3, [A9_NPipe]>],
1816 [4, 1, 2, 2, 3, 1]>,
1817 InstrItinData<IIC_VTBX4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1818 InstrStage<1, [A9_MUX0], 0>,
1819 InstrStage<1, [A9_DRegsN], 0, Required>,
1820 // Extra latency cycles since wbck is 8 cycles
1821 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1822 InstrStage<2, [A9_NPipe]>],
1823 [4, 1, 2, 2, 3, 3, 1]>