lib/Target/ARM/ARMScheduleA9.td

   1 //=- ARMScheduleA9.td - ARM Cortex-A9 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM Cortex A9 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
  16 // Reference Manual".
  17 //
  18 // Functional units
  19 def A9_Issue0  : FuncUnit; // Issue 0
  20 def A9_Issue1  : FuncUnit; // Issue 1
  21 def A9_Branch  : FuncUnit; // Branch
  22 def A9_ALU0    : FuncUnit; // ALU / MUL pipeline 0
  23 def A9_ALU1    : FuncUnit; // ALU pipeline 1
  24 def A9_AGU     : FuncUnit; // Address generation unit for ld / st
  25 def A9_NPipe   : FuncUnit; // NEON pipeline
  26 def A9_MUX0    : FuncUnit; // AGU + NEON/FPU multiplexer
  27 def A9_LSUnit  : FuncUnit; // L/S Unit
  28 def A9_DRegsVFP: FuncUnit; // FP register set, VFP side
  29 def A9_DRegsN  : FuncUnit; // FP register set, NEON side
  30
  31 // Bypasses
  32 def A9_LdBypass : Bypass;
  33
  34 def CortexA9Itineraries : ProcessorItineraries<
  35   [A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0,
  36    A9_LSUnit, A9_DRegsVFP, A9_DRegsN],
  37   [A9_LdBypass], [
  38   // Two fully-pipelined integer ALU pipelines
  39
  40   //
  41   // Move instructions, unconditional
  42   InstrItinData<IIC_iMOVi   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  43                                InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
  44   InstrItinData<IIC_iMOVr   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  45                                InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
  46   InstrItinData<IIC_iMOVsi  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  47                                InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
  48   InstrItinData<IIC_iMOVsr  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  49                                InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
  50   InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  51                                InstrStage<1, [A9_ALU0, A9_ALU1]>,
  52                                InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>,
  53   //
  54   // MVN instructions
  55   InstrItinData<IIC_iMVNi   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  56                                InstrStage<1, [A9_ALU0, A9_ALU1]>],
  57                               [1]>,
  58   InstrItinData<IIC_iMVNr   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  59                                InstrStage<1, [A9_ALU0, A9_ALU1]>],
  60                               [1, 1], [NoBypass, A9_LdBypass]>,
  61   InstrItinData<IIC_iMVNsi  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  62                                InstrStage<2, [A9_ALU0, A9_ALU1]>],
  63                               [2, 1]>,
  64   InstrItinData<IIC_iMVNsr  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  65                                InstrStage<3, [A9_ALU0, A9_ALU1]>],
  66                               [3, 1, 1]>,
  67   //
  68   // No operand cycles
  69   InstrItinData<IIC_iALUx   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  70                                InstrStage<1, [A9_ALU0, A9_ALU1]>]>,
  71   //
  72   // Binary Instructions that produce a result
  73   InstrItinData<IIC_iALUi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  74                              InstrStage<1, [A9_ALU0, A9_ALU1]>],
  75                             [1, 1], [NoBypass, A9_LdBypass]>,
  76   InstrItinData<IIC_iALUr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  77                              InstrStage<1, [A9_ALU0, A9_ALU1]>],
  78                             [1, 1, 1], [NoBypass, A9_LdBypass, A9_LdBypass]>,
  79   InstrItinData<IIC_iALUsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  80                              InstrStage<2, [A9_ALU0, A9_ALU1]>],
  81                             [2, 1, 1], [NoBypass, A9_LdBypass, NoBypass]>,
  82   InstrItinData<IIC_iALUsir,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  83                              InstrStage<2, [A9_ALU0, A9_ALU1]>],
  84                             [2, 1, 1], [NoBypass, NoBypass, A9_LdBypass]>,
  85   InstrItinData<IIC_iALUsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  86                              InstrStage<3, [A9_ALU0, A9_ALU1]>],
  87                             [3, 1, 1, 1],
  88                             [NoBypass, A9_LdBypass, NoBypass, NoBypass]>,
  89   //
  90   // Bitwise Instructions that produce a result
  91   InstrItinData<IIC_iBITi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  92                              InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
  93   InstrItinData<IIC_iBITr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  94                              InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
  95   InstrItinData<IIC_iBITsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  96                              InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
  97   InstrItinData<IIC_iBITsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
  98                              InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
  99   //
 100   // Unary Instructions that produce a result
 101
 102   // CLZ, RBIT, etc.
 103   InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 104                              InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
 105
 106   // BFC, BFI, UBFX, SBFX
 107   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 108                              InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1]>,
 109
 110   //
 111   // Zero and sign extension instructions
 112   InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 113                              InstrStage<1, [A9_ALU0, A9_ALU1]>], [2, 1]>,
 114   InstrItinData<IIC_iEXTAr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 115                              InstrStage<2, [A9_ALU0, A9_ALU1]>], [3, 1, 1]>,
 116   InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 117                              InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
 118   //
 119   // Compare instructions
 120   InstrItinData<IIC_iCMPi   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 121                                InstrStage<1, [A9_ALU0, A9_ALU1]>],
 122                                [1], [A9_LdBypass]>,
 123   InstrItinData<IIC_iCMPr   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 124                                InstrStage<1, [A9_ALU0, A9_ALU1]>],
 125                                [1, 1], [A9_LdBypass, A9_LdBypass]>,
 126   InstrItinData<IIC_iCMPsi  , [InstrStage<2, [A9_ALU0, A9_ALU1]>],
 127                                 [1, 1], [A9_LdBypass, NoBypass]>,
 128   InstrItinData<IIC_iCMPsr  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 129                                InstrStage<3, [A9_ALU0, A9_ALU1]>],
 130                               [1, 1, 1], [A9_LdBypass, NoBypass, NoBypass]>,
 131   //
 132   // Test instructions
 133   InstrItinData<IIC_iTSTi   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 134                                InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
 135   InstrItinData<IIC_iTSTr   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 136                                InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
 137   InstrItinData<IIC_iTSTsi  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 138                                InstrStage<2, [A9_ALU0, A9_ALU1]>], [1, 1]>,
 139   InstrItinData<IIC_iTSTsr  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 140                                InstrStage<3, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
 141   //
 142   // Move instructions, conditional
 143   // FIXME: Correctly model the extra input dep on the destination.
 144   InstrItinData<IIC_iCMOVi  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 145                                InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
 146   InstrItinData<IIC_iCMOVr  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 147                                InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
 148   InstrItinData<IIC_iCMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 149                                InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
 150   InstrItinData<IIC_iCMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 151                                InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
 152
 153   // Integer multiply pipeline
 154   //
 155   InstrItinData<IIC_iMUL16  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 156                                InstrStage<2, [A9_ALU0]>], [3, 1, 1]>,
 157   InstrItinData<IIC_iMAC16  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 158                                InstrStage<2, [A9_ALU0]>],
 159                               [3, 1, 1, 1]>,
 160   InstrItinData<IIC_iMUL32  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 161                                InstrStage<2, [A9_ALU0]>], [4, 1, 1]>,
 162   InstrItinData<IIC_iMAC32  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 163                                InstrStage<2, [A9_ALU0]>],
 164                               [4, 1, 1, 1]>,
 165   InstrItinData<IIC_iMUL64  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 166                                InstrStage<3, [A9_ALU0]>], [4, 5, 1, 1]>,
 167   InstrItinData<IIC_iMAC64  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 168                                InstrStage<3, [A9_ALU0]>],
 169                               [4, 5, 1, 1]>,
 170   // Integer load pipeline
 171   // FIXME: The timings are some rough approximations
 172   //
 173   // Immediate offset
 174   InstrItinData<IIC_iLoad_i   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 175                                  InstrStage<1, [A9_MUX0], 0>,
 176                                  InstrStage<1, [A9_AGU]>,
 177                                  InstrStage<1, [A9_LSUnit]>],
 178                                 [3, 1], [A9_LdBypass]>,
 179   InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 180                                  InstrStage<1, [A9_MUX0], 0>,
 181                                  InstrStage<2, [A9_AGU]>,
 182                                  InstrStage<1, [A9_LSUnit]>],
 183                                 [4, 1], [A9_LdBypass]>,
 184   // FIXME: If address is 64-bit aligned, AGU cycles is 1.
 185   InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 186                                  InstrStage<1, [A9_MUX0], 0>,
 187                                  InstrStage<2, [A9_AGU]>,
 188                                  InstrStage<1, [A9_LSUnit]>],
 189                                 [3, 3, 1], [A9_LdBypass]>,
 190   //
 191   // Register offset
 192   InstrItinData<IIC_iLoad_r   , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 193                                  InstrStage<1, [A9_MUX0], 0>,
 194                                  InstrStage<1, [A9_AGU]>,
 195                                  InstrStage<1, [A9_LSUnit]>],
 196                                 [3, 1, 1], [A9_LdBypass]>,
 197   InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 198                                  InstrStage<1, [A9_MUX0], 0>,
 199                                  InstrStage<2, [A9_AGU]>,
 200                                  InstrStage<1, [A9_LSUnit]>],
 201                                 [4, 1, 1], [A9_LdBypass]>,
 202   InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 203                                  InstrStage<1, [A9_MUX0], 0>,
 204                                  InstrStage<2, [A9_AGU]>,
 205                                  InstrStage<1, [A9_LSUnit]>],
 206                                 [3, 3, 1, 1], [A9_LdBypass]>,
 207   //
 208   // Scaled register offset
 209   InstrItinData<IIC_iLoad_si  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 210                                  InstrStage<1, [A9_MUX0], 0>,
 211                                  InstrStage<1, [A9_AGU]>,
 212                                  InstrStage<1, [A9_LSUnit]>],
 213                                 [4, 1, 1], [A9_LdBypass]>,
 214   InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 215                                  InstrStage<1, [A9_MUX0], 0>,
 216                                  InstrStage<2, [A9_AGU]>,
 217                                  InstrStage<1, [A9_LSUnit]>],
 218                                 [5, 1, 1], [A9_LdBypass]>,
 219   //
 220   // Immediate offset with update
 221   InstrItinData<IIC_iLoad_iu  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 222                                  InstrStage<1, [A9_MUX0], 0>,
 223                                  InstrStage<1, [A9_AGU]>,
 224                                  InstrStage<1, [A9_LSUnit]>],
 225                                 [3, 2, 1], [A9_LdBypass]>,
 226   InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 227                                  InstrStage<1, [A9_MUX0], 0>,
 228                                  InstrStage<2, [A9_AGU]>,
 229                                  InstrStage<1, [A9_LSUnit]>],
 230                                 [4, 3, 1], [A9_LdBypass]>,
 231   //
 232   // Register offset with update
 233   InstrItinData<IIC_iLoad_ru  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 234                                  InstrStage<1, [A9_MUX0], 0>,
 235                                  InstrStage<1, [A9_AGU]>,
 236                                  InstrStage<1, [A9_LSUnit]>],
 237                                 [3, 2, 1, 1], [A9_LdBypass]>,
 238   InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 239                                  InstrStage<1, [A9_MUX0], 0>,
 240                                  InstrStage<2, [A9_AGU]>,
 241                                  InstrStage<1, [A9_LSUnit]>],
 242                                 [4, 3, 1, 1], [A9_LdBypass]>,
 243   InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 244                                  InstrStage<1, [A9_MUX0], 0>,
 245                                  InstrStage<2, [A9_AGU]>,
 246                                  InstrStage<1, [A9_LSUnit]>],
 247                                 [3, 3, 1, 1], [A9_LdBypass]>,
 248   //
 249   // Scaled register offset with update
 250   InstrItinData<IIC_iLoad_siu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 251                                  InstrStage<1, [A9_MUX0], 0>,
 252                                  InstrStage<1, [A9_AGU]>,
 253                                  InstrStage<1, [A9_LSUnit]>],
 254                                 [4, 3, 1, 1], [A9_LdBypass]>,
 255   InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 256                                   InstrStage<1, [A9_MUX0], 0>,
 257                                   InstrStage<2, [A9_AGU]>,
 258                                   InstrStage<1, [A9_LSUnit]>],
 259                                  [5, 4, 1, 1], [A9_LdBypass]>,
 260   //
 261   // Load multiple, def is the 5th operand.
 262   // FIXME: This assumes 3 to 4 registers.
 263   InstrItinData<IIC_iLoad_m  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 264                                 InstrStage<1, [A9_MUX0], 0>,
 265                                 InstrStage<2, [A9_AGU], 1>,
 266                                 InstrStage<2, [A9_LSUnit]>],
 267                                [1, 1, 1, 1, 3],
 268                          [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
 269   //
 270   // Load multiple + update, defs are the 1st and 5th operands.
 271   InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 272                                 InstrStage<1, [A9_MUX0], 0>,
 273                                 InstrStage<2, [A9_AGU], 1>,
 274                                 InstrStage<2, [A9_LSUnit]>],
 275                                [2, 1, 1, 1, 3],
 276                          [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
 277   //
 278   // Load multiple plus branch
 279   InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 280                                 InstrStage<1, [A9_MUX0], 0>,
 281                                 InstrStage<1, [A9_AGU], 1>,
 282                                 InstrStage<2, [A9_LSUnit]>,
 283                                 InstrStage<1, [A9_Branch]>],
 284                                [1, 2, 1, 1, 3],
 285                          [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
 286   //
 287   // Pop, def is the 3rd operand.
 288   InstrItinData<IIC_iPop  ,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 289                                 InstrStage<1, [A9_MUX0], 0>,
 290                                 InstrStage<2, [A9_AGU], 1>,
 291                                 InstrStage<2, [A9_LSUnit]>],
 292                                [1, 1, 3],
 293                                [NoBypass, NoBypass, A9_LdBypass]>,
 294   //
 295   // Pop + branch, def is the 3rd operand.
 296   InstrItinData<IIC_iPop_Br,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 297                                 InstrStage<1, [A9_MUX0], 0>,
 298                                 InstrStage<2, [A9_AGU], 1>,
 299                                 InstrStage<2, [A9_LSUnit]>,
 300                                 InstrStage<1, [A9_Branch]>],
 301                                [1, 1, 3],
 302                                [NoBypass, NoBypass, A9_LdBypass]>,
 303
 304   //
 305   // iLoadi + iALUr for t2LDRpci_pic.
 306   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 307                                 InstrStage<1, [A9_MUX0], 0>,
 308                                 InstrStage<1, [A9_AGU]>,
 309                                 InstrStage<1, [A9_LSUnit]>,
 310                                 InstrStage<1, [A9_ALU0, A9_ALU1]>],
 311                                [2, 1]>,
 312
 313   // Integer store pipeline
 314   ///
 315   // Immediate offset
 316   InstrItinData<IIC_iStore_i  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 317                                  InstrStage<1, [A9_MUX0], 0>,
 318                                  InstrStage<1, [A9_AGU]>,
 319                                  InstrStage<1, [A9_LSUnit]>], [1, 1]>,
 320   InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 321                                  InstrStage<1, [A9_MUX0], 0>,
 322                                  InstrStage<2, [A9_AGU], 1>,
 323                                  InstrStage<1, [A9_LSUnit]>], [1, 1]>,
 324   // FIXME: If address is 64-bit aligned, AGU cycles is 1.
 325   InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 326                                  InstrStage<1, [A9_MUX0], 0>,
 327                                  InstrStage<2, [A9_AGU], 1>,
 328                                  InstrStage<1, [A9_LSUnit]>], [1, 1]>,
 329   //
 330   // Register offset
 331   InstrItinData<IIC_iStore_r  , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 332                                  InstrStage<1, [A9_MUX0], 0>,
 333                                  InstrStage<1, [A9_AGU]>,
 334                                  InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
 335   InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 336                                  InstrStage<1, [A9_MUX0], 0>,
 337                                  InstrStage<2, [A9_AGU], 1>,
 338                                  InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
 339   InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 340                                  InstrStage<1, [A9_MUX0], 0>,
 341                                  InstrStage<2, [A9_AGU], 1>,
 342                                  InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
 343   //
 344   // Scaled register offset
 345   InstrItinData<IIC_iStore_si ,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 346                                   InstrStage<1, [A9_MUX0], 0>,
 347                                   InstrStage<1, [A9_AGU]>,
 348                                   InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
 349   InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 350                                   InstrStage<1, [A9_MUX0], 0>,
 351                                   InstrStage<2, [A9_AGU], 1>,
 352                                   InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
 353   //
 354   // Immediate offset with update
 355   InstrItinData<IIC_iStore_iu ,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 356                                   InstrStage<1, [A9_MUX0], 0>,
 357                                   InstrStage<1, [A9_AGU]>,
 358                                   InstrStage<1, [A9_LSUnit]>], [2, 1, 1]>,
 359   InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 360                                   InstrStage<1, [A9_MUX0], 0>,
 361                                   InstrStage<2, [A9_AGU], 1>,
 362                                   InstrStage<1, [A9_LSUnit]>], [3, 1, 1]>,
 363   //
 364   // Register offset with update
 365   InstrItinData<IIC_iStore_ru ,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 366                                   InstrStage<1, [A9_MUX0], 0>,
 367                                   InstrStage<1, [A9_AGU]>,
 368                                   InstrStage<1, [A9_LSUnit]>],
 369                                  [2, 1, 1, 1]>,
 370   InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 371                                   InstrStage<1, [A9_MUX0], 0>,
 372                                   InstrStage<2, [A9_AGU], 1>,
 373                                   InstrStage<1, [A9_LSUnit]>],
 374                                  [3, 1, 1, 1]>,
 375   InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 376                                   InstrStage<1, [A9_MUX0], 0>,
 377                                   InstrStage<2, [A9_AGU], 1>,
 378                                   InstrStage<1, [A9_LSUnit]>],
 379                                  [3, 1, 1, 1]>,
 380   //
 381   // Scaled register offset with update
 382   InstrItinData<IIC_iStore_siu,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 383                                     InstrStage<1, [A9_MUX0], 0>,
 384                                     InstrStage<1, [A9_AGU]>,
 385                                     InstrStage<1, [A9_LSUnit]>],
 386                                    [2, 1, 1, 1]>,
 387   InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 388                                     InstrStage<1, [A9_MUX0], 0>,
 389                                     InstrStage<2, [A9_AGU], 1>,
 390                                     InstrStage<1, [A9_LSUnit]>],
 391                                    [3, 1, 1, 1]>,
 392   //
 393   // Store multiple
 394   InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 395                                 InstrStage<1, [A9_MUX0], 0>,
 396                                 InstrStage<1, [A9_AGU]>,
 397                                 InstrStage<2, [A9_LSUnit]>]>,
 398   //
 399   // Store multiple + update
 400   InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 401                                 InstrStage<1, [A9_MUX0], 0>,
 402                                 InstrStage<1, [A9_AGU]>,
 403                                 InstrStage<2, [A9_LSUnit]>], [2]>,
 404
 405   // Branch
 406   //
 407   // no delay slots, so the latency of a branch is unimportant
 408   InstrItinData<IIC_Br       , [InstrStage<1, [A9_Issue0], 0>,
 409                                 InstrStage<1, [A9_Issue1], 0>,
 410                                 InstrStage<1, [A9_Branch]>]>,
 411
 412   // VFP and NEON shares the same register file. This means that every VFP
 413   // instruction should wait for full completion of the consecutive NEON
 414   // instruction and vice-versa. We model this behavior with two artificial FUs:
 415   // DRegsVFP and DRegsVFP.
 416   //
 417   // Every VFP instruction:
 418   //  - Acquires DRegsVFP resource for 1 cycle
 419   //  - Reserves DRegsN resource for the whole duration (including time to
 420   //    register file writeback!).
 421   // Every NEON instruction does the same but with FUs swapped.
 422   //
 423   // Since the reserved FU cannot be acquired, this models precisely
 424   // "cross-domain" stalls.
 425
 426   // VFP
 427   // Issue through integer pipeline, and execute in NEON unit.
 428
 429   // FP Special Register to Integer Register File Move
 430   InstrItinData<IIC_fpSTAT , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 431                               InstrStage<1, [A9_MUX0], 0>,
 432                               InstrStage<1, [A9_DRegsVFP], 0, Required>,
 433                               InstrStage<2, [A9_DRegsN],   0, Reserved>,
 434                               InstrStage<1, [A9_NPipe]>],
 435                              [1]>,
 436   //
 437   // Single-precision FP Unary
 438   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 439                                InstrStage<1, [A9_MUX0], 0>,
 440                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 441                                // Extra latency cycles since wbck is 2 cycles
 442                                InstrStage<3, [A9_DRegsN],   0, Reserved>,
 443                                InstrStage<1, [A9_NPipe]>],
 444                               [1, 1]>,
 445   //
 446   // Double-precision FP Unary
 447   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 448                                InstrStage<1, [A9_MUX0], 0>,
 449                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 450                                // Extra latency cycles since wbck is 2 cycles
 451                                InstrStage<3, [A9_DRegsN],   0, Reserved>,
 452                                InstrStage<1, [A9_NPipe]>],
 453                               [1, 1]>,
 454
 455   //
 456   // Single-precision FP Compare
 457   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 458                                InstrStage<1, [A9_MUX0], 0>,
 459                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 460                                // Extra latency cycles since wbck is 4 cycles
 461                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 462                                InstrStage<1, [A9_NPipe]>],
 463                               [1, 1]>,
 464   //
 465   // Double-precision FP Compare
 466   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 467                                InstrStage<1, [A9_MUX0], 0>,
 468                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 469                                // Extra latency cycles since wbck is 4 cycles
 470                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 471                                InstrStage<1, [A9_NPipe]>],
 472                               [1, 1]>,
 473   //
 474   // Single to Double FP Convert
 475   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 476                                InstrStage<1, [A9_MUX0], 0>,
 477                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 478                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 479                                InstrStage<1, [A9_NPipe]>],
 480                               [4, 1]>,
 481   //
 482   // Double to Single FP Convert
 483   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 484                                InstrStage<1, [A9_MUX0], 0>,
 485                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 486                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 487                                InstrStage<1, [A9_NPipe]>],
 488                               [4, 1]>,
 489
 490   //
 491   // Single to Half FP Convert
 492   InstrItinData<IIC_fpCVTSH , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 493                                InstrStage<1, [A9_MUX0], 0>,
 494                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 495                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 496                                InstrStage<1, [A9_NPipe]>],
 497                               [4, 1]>,
 498   //
 499   // Half to Single FP Convert
 500   InstrItinData<IIC_fpCVTHS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 501                                InstrStage<1, [A9_MUX0], 0>,
 502                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 503                                InstrStage<3, [A9_DRegsN],   0, Reserved>,
 504                                InstrStage<1, [A9_NPipe]>],
 505                               [2, 1]>,
 506
 507   //
 508   // Single-Precision FP to Integer Convert
 509   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 510                                InstrStage<1, [A9_MUX0], 0>,
 511                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 512                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 513                                InstrStage<1, [A9_NPipe]>],
 514                               [4, 1]>,
 515   //
 516   // Double-Precision FP to Integer Convert
 517   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 518                                InstrStage<1, [A9_MUX0], 0>,
 519                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 520                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 521                                InstrStage<1, [A9_NPipe]>],
 522                               [4, 1]>,
 523   //
 524   // Integer to Single-Precision FP Convert
 525   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 526                                InstrStage<1, [A9_MUX0], 0>,
 527                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 528                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 529                                InstrStage<1, [A9_NPipe]>],
 530                               [4, 1]>,
 531   //
 532   // Integer to Double-Precision FP Convert
 533   InstrItinData<IIC_fpCVTID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 534                                InstrStage<1, [A9_MUX0], 0>,
 535                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 536                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 537                                InstrStage<1, [A9_NPipe]>],
 538                               [4, 1]>,
 539   //
 540   // Single-precision FP ALU
 541   InstrItinData<IIC_fpALU32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 542                                InstrStage<1, [A9_MUX0], 0>,
 543                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 544                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 545                                InstrStage<1, [A9_NPipe]>],
 546                               [4, 1, 1]>,
 547   //
 548   // Double-precision FP ALU
 549   InstrItinData<IIC_fpALU64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 550                                InstrStage<1, [A9_MUX0], 0>,
 551                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 552                                InstrStage<5, [A9_DRegsN],   0, Reserved>,
 553                                InstrStage<1, [A9_NPipe]>],
 554                               [4, 1, 1]>,
 555   //
 556   // Single-precision FP Multiply
 557   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 558                                InstrStage<1, [A9_MUX0], 0>,
 559                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 560                                InstrStage<6, [A9_DRegsN],   0, Reserved>,
 561                                InstrStage<1, [A9_NPipe]>],
 562                               [5, 1, 1]>,
 563   //
 564   // Double-precision FP Multiply
 565   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 566                                InstrStage<1, [A9_MUX0], 0>,
 567                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 568                                InstrStage<7, [A9_DRegsN],   0, Reserved>,
 569                                InstrStage<2, [A9_NPipe]>],
 570                               [6, 1, 1]>,
 571   //
 572   // Single-precision FP MAC
 573   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 574                                InstrStage<1, [A9_MUX0], 0>,
 575                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 576                                InstrStage<9, [A9_DRegsN],   0, Reserved>,
 577                                InstrStage<1, [A9_NPipe]>],
 578                               [8, 1, 1, 1]>,
 579   //
 580   // Double-precision FP MAC
 581   InstrItinData<IIC_fpMAC64 , [InstrStage<1,  [A9_Issue0, A9_Issue1], 0>,
 582                                InstrStage<1,  [A9_MUX0], 0>,
 583                                InstrStage<1,  [A9_DRegsVFP], 0, Required>,
 584                                InstrStage<10, [A9_DRegsN],  0, Reserved>,
 585                                InstrStage<2,  [A9_NPipe]>],
 586                               [9, 1, 1, 1]>,
 587   //
 588   // Single-precision FP DIV
 589   InstrItinData<IIC_fpDIV32 , [InstrStage<1,  [A9_Issue0, A9_Issue1], 0>,
 590                                InstrStage<1,  [A9_MUX0], 0>,
 591                                InstrStage<1,  [A9_DRegsVFP], 0, Required>,
 592                                InstrStage<16, [A9_DRegsN],  0, Reserved>,
 593                                InstrStage<10, [A9_NPipe]>],
 594                               [15, 1, 1]>,
 595   //
 596   // Double-precision FP DIV
 597   InstrItinData<IIC_fpDIV64 , [InstrStage<1,  [A9_Issue0, A9_Issue1], 0>,
 598                                InstrStage<1,  [A9_MUX0], 0>,
 599                                InstrStage<1,  [A9_DRegsVFP], 0, Required>,
 600                                InstrStage<26, [A9_DRegsN],  0, Reserved>,
 601                                InstrStage<20, [A9_NPipe]>],
 602                               [25, 1, 1]>,
 603   //
 604   // Single-precision FP SQRT
 605   InstrItinData<IIC_fpSQRT32, [InstrStage<1,  [A9_Issue0, A9_Issue1], 0>,
 606                                InstrStage<1,  [A9_MUX0], 0>,
 607                                InstrStage<1,  [A9_DRegsVFP], 0, Required>,
 608                                InstrStage<18, [A9_DRegsN],   0, Reserved>,
 609                                InstrStage<13, [A9_NPipe]>],
 610                               [17, 1]>,
 611   //
 612   // Double-precision FP SQRT
 613   InstrItinData<IIC_fpSQRT64, [InstrStage<1,  [A9_Issue0, A9_Issue1], 0>,
 614                                InstrStage<1,  [A9_MUX0], 0>,
 615                                InstrStage<1,  [A9_DRegsVFP], 0, Required>,
 616                                InstrStage<33, [A9_DRegsN],   0, Reserved>,
 617                                InstrStage<28, [A9_NPipe]>],
 618                               [32, 1]>,
 619
 620   //
 621   // Integer to Single-precision Move
 622   InstrItinData<IIC_fpMOVIS,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 623                                InstrStage<1, [A9_MUX0], 0>,
 624                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 625                                // Extra 1 latency cycle since wbck is 2 cycles
 626                                InstrStage<3, [A9_DRegsN],   0, Reserved>,
 627                                InstrStage<1, [A9_NPipe]>],
 628                               [1, 1]>,
 629   //
 630   // Integer to Double-precision Move
 631   InstrItinData<IIC_fpMOVID,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 632                                InstrStage<1, [A9_MUX0], 0>,
 633                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 634                                // Extra 1 latency cycle since wbck is 2 cycles
 635                                InstrStage<3, [A9_DRegsN],   0, Reserved>,
 636                                InstrStage<1, [A9_NPipe]>],
 637                               [1, 1, 1]>,
 638   //
 639   // Single-precision to Integer Move
 640   InstrItinData<IIC_fpMOVSI,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 641                                InstrStage<1, [A9_MUX0], 0>,
 642                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 643                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 644                                InstrStage<1, [A9_NPipe]>],
 645                               [2, 1]>,
 646   //
 647   // Double-precision to Integer Move
 648   InstrItinData<IIC_fpMOVDI,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 649                                InstrStage<1, [A9_MUX0], 0>,
 650                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 651                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 652                                InstrStage<1, [A9_NPipe]>],
 653                               [2, 1, 1]>,
 654   //
 655   // Single-precision FP Load
 656   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 657                                InstrStage<1, [A9_MUX0], 0>,
 658                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 659                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 660                                InstrStage<1, [A9_NPipe]>,
 661                                InstrStage<1, [A9_LSUnit]>],
 662                               [1, 1]>,
 663   //
 664   // Double-precision FP Load
 665   // FIXME: Result latency is 1 if address is 64-bit aligned.
 666   InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 667                                InstrStage<1, [A9_MUX0], 0>,
 668                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 669                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 670                                InstrStage<1, [A9_NPipe]>,
 671                                InstrStage<1, [A9_LSUnit]>],
 672                               [2, 1]>,
 673   //
 674   // FP Load Multiple
 675   InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 676                                InstrStage<1, [A9_MUX0], 0>,
 677                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 678                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 679                                InstrStage<1, [A9_NPipe]>,
 680                                InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>,
 681   //
 682   // FP Load Multiple + update
 683   InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 684                                InstrStage<1, [A9_MUX0], 0>,
 685                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 686                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 687                                InstrStage<1, [A9_NPipe]>,
 688                                InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>,
 689   //
 690   // Single-precision FP Store
 691   InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 692                                InstrStage<1, [A9_MUX0], 0>,
 693                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 694                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 695                                InstrStage<1, [A9_NPipe]>,
 696                                InstrStage<1, [A9_LSUnit]>],
 697                               [1, 1]>,
 698   //
 699   // Double-precision FP Store
 700   InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 701                                InstrStage<1, [A9_MUX0], 0>,
 702                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 703                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 704                                InstrStage<1, [A9_NPipe]>,
 705                                InstrStage<1, [A9_LSUnit]>],
 706                               [1, 1]>,
 707   //
 708   // FP Store Multiple
 709   InstrItinData<IIC_fpStore_m,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 710                                InstrStage<1, [A9_MUX0], 0>,
 711                                InstrStage<1, [A9_DRegsVFP], 0, Required>,
 712                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
 713                                InstrStage<1, [A9_NPipe]>,
 714                                InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>,
 715   //
 716   // FP Store Multiple + update
 717   InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 718                                 InstrStage<1, [A9_MUX0], 0>,
 719                                 InstrStage<1, [A9_DRegsVFP], 0, Required>,
 720                                 InstrStage<2, [A9_DRegsN],   0, Reserved>,
 721                                 InstrStage<1, [A9_NPipe]>,
 722                                 InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>,
 723   // NEON
 724   // VLD1
 725   // FIXME: Conservatively assume insufficent alignment.
 726   InstrItinData<IIC_VLD1,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 727                                InstrStage<1, [A9_MUX0], 0>,
 728                                InstrStage<1, [A9_DRegsN],   0, Required>,
 729                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 730                                InstrStage<2, [A9_NPipe], 1>,
 731                                InstrStage<2, [A9_LSUnit]>],
 732                               [2, 1]>,
 733   // VLD1x2
 734   InstrItinData<IIC_VLD1x2,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 735                                InstrStage<1, [A9_MUX0], 0>,
 736                                InstrStage<1, [A9_DRegsN],   0, Required>,
 737                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 738                                InstrStage<2, [A9_NPipe], 1>,
 739                                InstrStage<2, [A9_LSUnit]>],
 740                               [2, 2, 1]>,
 741   // VLD1x3
 742   InstrItinData<IIC_VLD1x3,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 743                                InstrStage<1, [A9_MUX0], 0>,
 744                                InstrStage<1, [A9_DRegsN],   0, Required>,
 745                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 746                                InstrStage<3, [A9_NPipe], 1>,
 747                                InstrStage<3, [A9_LSUnit]>],
 748                               [2, 2, 3, 1]>,
 749   // VLD1x4
 750   InstrItinData<IIC_VLD1x4,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 751                                InstrStage<1, [A9_MUX0], 0>,
 752                                InstrStage<1, [A9_DRegsN],   0, Required>,
 753                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 754                                InstrStage<3, [A9_NPipe], 1>,
 755                                InstrStage<3, [A9_LSUnit]>],
 756                               [2, 2, 3, 3, 1]>,
 757   // VLD1u
 758   InstrItinData<IIC_VLD1u,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 759                                InstrStage<1, [A9_MUX0], 0>,
 760                                InstrStage<1, [A9_DRegsN],   0, Required>,
 761                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 762                                InstrStage<2, [A9_NPipe], 1>,
 763                                InstrStage<2, [A9_LSUnit]>],
 764                               [2, 2, 1]>,
 765   // VLD1x2u
 766   InstrItinData<IIC_VLD1x2u,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 767                                InstrStage<1, [A9_MUX0], 0>,
 768                                InstrStage<1, [A9_DRegsN],   0, Required>,
 769                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 770                                InstrStage<2, [A9_NPipe], 1>,
 771                                InstrStage<2, [A9_LSUnit]>],
 772                               [2, 2, 2, 1]>,
 773   // VLD1x3u
 774   InstrItinData<IIC_VLD1x3u,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 775                                InstrStage<1, [A9_MUX0], 0>,
 776                                InstrStage<1, [A9_DRegsN],   0, Required>,
 777                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 778                                InstrStage<3, [A9_NPipe], 1>,
 779                                InstrStage<3, [A9_LSUnit]>],
 780                               [2, 2, 3, 2, 1]>,
 781   // VLD1x4u
 782   InstrItinData<IIC_VLD1x4u,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 783                                InstrStage<1, [A9_MUX0], 0>,
 784                                InstrStage<1, [A9_DRegsN],   0, Required>,
 785                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 786                                InstrStage<3, [A9_NPipe], 1>,
 787                                InstrStage<3, [A9_LSUnit]>],
 788                               [2, 2, 3, 3, 2, 1]>,
 789   //
 790   // VLD1ln
 791   InstrItinData<IIC_VLD1ln,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 792                                InstrStage<1, [A9_MUX0], 0>,
 793                                InstrStage<1, [A9_DRegsN],   0, Required>,
 794                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 795                                InstrStage<3, [A9_NPipe], 1>,
 796                                InstrStage<3, [A9_LSUnit]>],
 797                               [4, 1, 1, 1]>,
 798   //
 799   // VLD1lnu
 800   InstrItinData<IIC_VLD1lnu,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 801                                InstrStage<1, [A9_MUX0], 0>,
 802                                InstrStage<1, [A9_DRegsN],   0, Required>,
 803                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 804                                InstrStage<3, [A9_NPipe], 1>,
 805                                InstrStage<3, [A9_LSUnit]>],
 806                               [4, 2, 1, 1, 1, 1]>,
 807   //
 808   // VLD2
 809   InstrItinData<IIC_VLD2,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 810                                InstrStage<1, [A9_MUX0], 0>,
 811                                InstrStage<1, [A9_DRegsN],   0, Required>,
 812                                // Extra latency cycles since wbck is 7 cycles
 813                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 814                                InstrStage<2, [A9_NPipe], 1>,
 815                                InstrStage<2, [A9_LSUnit]>],
 816                               [3, 3, 1]>,
 817   //
 818   // VLD2x2
 819   InstrItinData<IIC_VLD2x2,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 820                                InstrStage<1, [A9_MUX0], 0>,
 821                                InstrStage<1, [A9_DRegsN],   0, Required>,
 822                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 823                                InstrStage<3, [A9_NPipe], 1>,
 824                                InstrStage<3, [A9_LSUnit]>],
 825                               [3, 4, 3, 4, 1]>,
 826   //
 827   // VLD2ln
 828   InstrItinData<IIC_VLD2ln,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 829                                InstrStage<1, [A9_MUX0], 0>,
 830                                InstrStage<1, [A9_DRegsN],   0, Required>,
 831                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 832                                InstrStage<3, [A9_NPipe], 1>,
 833                                InstrStage<3, [A9_LSUnit]>],
 834                               [4, 4, 1, 1, 1, 1]>,
 835   //
 836   // VLD2u
 837   InstrItinData<IIC_VLD2u,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 838                                InstrStage<1, [A9_MUX0], 0>,
 839                                InstrStage<1, [A9_DRegsN],   0, Required>,
 840                                // Extra latency cycles since wbck is 7 cycles
 841                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
 842                                InstrStage<2, [A9_NPipe], 1>,
 843                                InstrStage<2, [A9_LSUnit]>],
 844                               [3, 3, 2, 1, 1, 1]>,
 845   //
 846   // VLD2x2u
 847   InstrItinData<IIC_VLD2x2u,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 848                                InstrStage<1, [A9_MUX0], 0>,
 849                                InstrStage<1, [A9_DRegsN],   0, Required>,
 850                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 851                                InstrStage<3, [A9_NPipe], 1>,
 852                                InstrStage<3, [A9_LSUnit]>],
 853                               [3, 4, 3, 4, 2, 1]>,
 854   //
 855   // VLD2lnu
 856   InstrItinData<IIC_VLD2lnu,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 857                                InstrStage<1, [A9_MUX0], 0>,
 858                                InstrStage<1, [A9_DRegsN],   0, Required>,
 859                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
 860                                InstrStage<3, [A9_NPipe], 1>,
 861                                InstrStage<3, [A9_LSUnit]>],
 862                               [4, 4, 2, 1, 1, 1, 1, 1]>,
 863   //
 864   // VLD3
 865   InstrItinData<IIC_VLD3,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 866                                InstrStage<1, [A9_MUX0], 0>,
 867                                InstrStage<1, [A9_DRegsN],   0, Required>,
 868                                InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
 869                                InstrStage<4, [A9_NPipe], 1>,
 870                                InstrStage<4, [A9_LSUnit]>],
 871                               [4, 4, 5, 1]>,
 872   //
 873   // VLD3ln
 874   InstrItinData<IIC_VLD3ln,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 875                                InstrStage<1, [A9_MUX0], 0>,
 876                                InstrStage<1, [A9_DRegsN],   0, Required>,
 877                                InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
 878                                InstrStage<5, [A9_NPipe], 1>,
 879                                InstrStage<5, [A9_LSUnit]>],
 880                               [5, 5, 6, 1, 1, 1, 1, 2]>,
 881   //
 882   // VLD3u
 883   InstrItinData<IIC_VLD3u,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 884                                InstrStage<1, [A9_MUX0], 0>,
 885                                InstrStage<1, [A9_DRegsN],   0, Required>,
 886                                InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
 887                                InstrStage<4, [A9_NPipe], 1>,
 888                                InstrStage<4, [A9_LSUnit]>],
 889                               [4, 4, 5, 2, 1]>,
 890   //
 891   // VLD3lnu
 892   InstrItinData<IIC_VLD3lnu,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 893                                InstrStage<1, [A9_MUX0], 0>,
 894                                InstrStage<1, [A9_DRegsN],   0, Required>,
 895                                InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
 896                                InstrStage<5, [A9_NPipe], 1>,
 897                                InstrStage<5, [A9_LSUnit]>],
 898                               [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>,
 899   //
 900   // VLD4
 901   InstrItinData<IIC_VLD4,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 902                                InstrStage<1, [A9_MUX0], 0>,
 903                                InstrStage<1, [A9_DRegsN],   0, Required>,
 904                                InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
 905                                InstrStage<4, [A9_NPipe], 1>,
 906                                InstrStage<4, [A9_LSUnit]>],
 907                               [4, 4, 5, 5, 1]>,
 908   //
 909   // VLD4ln
 910   InstrItinData<IIC_VLD4ln,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 911                                InstrStage<1, [A9_MUX0], 0>,
 912                                InstrStage<1, [A9_DRegsN],   0, Required>,
 913                                InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
 914                                InstrStage<5, [A9_NPipe], 1>,
 915                                InstrStage<5, [A9_LSUnit]>],
 916                               [5, 5, 6, 6, 1, 1, 1, 1, 2, 2]>,
 917   //
 918   // VLD4u
 919   InstrItinData<IIC_VLD4u,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 920                                InstrStage<1, [A9_MUX0], 0>,
 921                                InstrStage<1, [A9_DRegsN],   0, Required>,
 922                                InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
 923                                InstrStage<4, [A9_NPipe], 1>,
 924                                InstrStage<4, [A9_LSUnit]>],
 925                               [4, 4, 5, 5, 2, 1]>,
 926   //
 927   // VLD4lnu
 928   InstrItinData<IIC_VLD4lnu,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 929                                InstrStage<1, [A9_MUX0], 0>,
 930                                InstrStage<1, [A9_DRegsN],   0, Required>,
 931                                InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
 932                                InstrStage<5, [A9_NPipe], 1>,
 933                                InstrStage<5, [A9_LSUnit]>],
 934                               [5, 5, 6, 6, 2, 1, 1, 1, 1, 1, 2, 2]>,
 935   //
 936   // VST1
 937   InstrItinData<IIC_VST1,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 938                                InstrStage<1, [A9_MUX0], 0>,
 939                                InstrStage<1, [A9_DRegsN],   0, Required>,
 940                                InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
 941                                InstrStage<2, [A9_NPipe], 1>,
 942                                InstrStage<2, [A9_LSUnit]>],
 943                               [1, 1, 1]>,
 944   //
 945   // VST1x2
 946   InstrItinData<IIC_VST1x2,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 947                                InstrStage<1, [A9_MUX0], 0>,
 948                                InstrStage<1, [A9_DRegsN],   0, Required>,
 949                                InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
 950                                InstrStage<2, [A9_NPipe], 1>,
 951                                InstrStage<2, [A9_LSUnit]>],
 952                               [1, 1, 1, 1]>,
 953   //
 954   // VST1x3
 955   InstrItinData<IIC_VST1x3,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 956                                InstrStage<1, [A9_MUX0], 0>,
 957                                InstrStage<1, [A9_DRegsN],   0, Required>,
 958                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
 959                                InstrStage<3, [A9_NPipe], 1>,
 960                                InstrStage<3, [A9_LSUnit]>],
 961                               [1, 1, 1, 1, 2]>,
 962   //
 963   // VST1x4
 964   InstrItinData<IIC_VST1x4,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 965                                InstrStage<1, [A9_MUX0], 0>,
 966                                InstrStage<1, [A9_DRegsN],   0, Required>,
 967                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
 968                                InstrStage<3, [A9_NPipe], 1>,
 969                                InstrStage<3, [A9_LSUnit]>],
 970                               [1, 1, 1, 1, 2, 2]>,
 971   //
 972   // VST1u
 973   InstrItinData<IIC_VST1u,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 974                                InstrStage<1, [A9_MUX0], 0>,
 975                                InstrStage<1, [A9_DRegsN],   0, Required>,
 976                                InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
 977                                InstrStage<2, [A9_NPipe], 1>,
 978                                InstrStage<2, [A9_LSUnit]>],
 979                               [2, 1, 1, 1, 1]>,
 980   //
 981   // VST1x2u
 982   InstrItinData<IIC_VST1x2u,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 983                                InstrStage<1, [A9_MUX0], 0>,
 984                                InstrStage<1, [A9_DRegsN],   0, Required>,
 985                                InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
 986                                InstrStage<2, [A9_NPipe], 1>,
 987                                InstrStage<2, [A9_LSUnit]>],
 988                               [2, 1, 1, 1, 1, 1]>,
 989   //
 990   // VST1x3u
 991   InstrItinData<IIC_VST1x3u,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
 992                                InstrStage<1, [A9_MUX0], 0>,
 993                                InstrStage<1, [A9_DRegsN],   0, Required>,
 994                                InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
 995                                InstrStage<3, [A9_NPipe], 1>,
 996                                InstrStage<3, [A9_LSUnit]>],
 997                               [2, 1, 1, 1, 1, 1, 2]>,
 998   //
 999   // VST1x4u
1000   InstrItinData<IIC_VST1x4u,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1001                                InstrStage<1, [A9_MUX0], 0>,
1002                                InstrStage<1, [A9_DRegsN],   0, Required>,
1003                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1004                                InstrStage<3, [A9_NPipe], 1>,
1005                                InstrStage<3, [A9_LSUnit]>],
1006                               [2, 1, 1, 1, 1, 1, 2, 2]>,
1007   //
1008   // VST2
1009   InstrItinData<IIC_VST2,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1010                                InstrStage<1, [A9_MUX0], 0>,
1011                                InstrStage<1, [A9_DRegsN],   0, Required>,
1012                                InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1013                                InstrStage<2, [A9_NPipe], 1>,
1014                                InstrStage<2, [A9_LSUnit]>],
1015                               [1, 1, 1, 1]>,
1016   //
1017   // VST2x2
1018   InstrItinData<IIC_VST2x2,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1019                                InstrStage<1, [A9_MUX0], 0>,
1020                                InstrStage<1, [A9_DRegsN],   0, Required>,
1021                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1022                                InstrStage<3, [A9_NPipe], 1>,
1023                                InstrStage<3, [A9_LSUnit]>],
1024                               [1, 1, 1, 1, 2, 2]>,
1025   //
1026   // VST2u
1027   InstrItinData<IIC_VST2u,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1028                                InstrStage<1, [A9_MUX0], 0>,
1029                                InstrStage<1, [A9_DRegsN],   0, Required>,
1030                                InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1031                                InstrStage<2, [A9_NPipe], 1>,
1032                                InstrStage<2, [A9_LSUnit]>],
1033                               [2, 1, 1, 1, 1, 1]>,
1034   //
1035   // VST2x2u
1036   InstrItinData<IIC_VST2x2u,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1037                                InstrStage<1, [A9_MUX0], 0>,
1038                                InstrStage<1, [A9_DRegsN],   0, Required>,
1039                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1040                                InstrStage<3, [A9_NPipe], 1>,
1041                                InstrStage<3, [A9_LSUnit]>],
1042                               [2, 1, 1, 1, 1, 1, 2, 2]>,
1043   //
1044   // VST2ln
1045   InstrItinData<IIC_VST2ln,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1046                                InstrStage<1, [A9_MUX0], 0>,
1047                                InstrStage<1, [A9_DRegsN],   0, Required>,
1048                                InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1049                                InstrStage<2, [A9_NPipe], 1>,
1050                                InstrStage<2, [A9_LSUnit]>],
1051                               [1, 1, 1, 1]>,
1052   //
1053   // VST2lnu
1054   InstrItinData<IIC_VST2lnu,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1055                                InstrStage<1, [A9_MUX0], 0>,
1056                                InstrStage<1, [A9_DRegsN],   0, Required>,
1057                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1058                                InstrStage<3, [A9_NPipe], 1>,
1059                                InstrStage<3, [A9_LSUnit]>],
1060                               [2, 1, 1, 1, 1, 1]>,
1061   //
1062   // VST3
1063   InstrItinData<IIC_VST3,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1064                                InstrStage<1, [A9_MUX0], 0>,
1065                                InstrStage<1, [A9_DRegsN],   0, Required>,
1066                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1067                                InstrStage<3, [A9_NPipe], 1>,
1068                                InstrStage<3, [A9_LSUnit]>],
1069                               [1, 1, 1, 1, 2]>,
1070   //
1071   // VST3u
1072   InstrItinData<IIC_VST3u,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1073                                InstrStage<1, [A9_MUX0], 0>,
1074                                InstrStage<1, [A9_DRegsN],   0, Required>,
1075                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1076                                InstrStage<3, [A9_NPipe], 1>,
1077                                InstrStage<3, [A9_LSUnit]>],
1078                               [2, 1, 1, 1, 1, 1, 2]>,
1079   //
1080   // VST3ln
1081   InstrItinData<IIC_VST3ln,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1082                                InstrStage<1, [A9_MUX0], 0>,
1083                                InstrStage<1, [A9_DRegsN],   0, Required>,
1084                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1085                                InstrStage<3, [A9_NPipe], 1>,
1086                                InstrStage<3, [A9_LSUnit]>],
1087                               [1, 1, 1, 1, 2]>,
1088   //
1089   // VST3lnu
1090   InstrItinData<IIC_VST3lnu,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1091                                InstrStage<1, [A9_MUX0], 0>,
1092                                InstrStage<1, [A9_DRegsN],   0, Required>,
1093                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1094                                InstrStage<3, [A9_NPipe], 1>,
1095                                InstrStage<3, [A9_LSUnit]>],
1096                               [2, 1, 1, 1, 1, 1, 2]>,
1097   //
1098   // VST4
1099   InstrItinData<IIC_VST4,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1100                                InstrStage<1, [A9_MUX0], 0>,
1101                                InstrStage<1, [A9_DRegsN],   0, Required>,
1102                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1103                                InstrStage<3, [A9_NPipe], 1>,
1104                                InstrStage<3, [A9_LSUnit]>],
1105                               [1, 1, 1, 1, 2, 2]>,
1106   //
1107   // VST4u
1108   InstrItinData<IIC_VST4u,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1109                                InstrStage<1, [A9_MUX0], 0>,
1110                                InstrStage<1, [A9_DRegsN],   0, Required>,
1111                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1112                                InstrStage<3, [A9_NPipe], 1>,
1113                                InstrStage<3, [A9_LSUnit]>],
1114                               [2, 1, 1, 1, 1, 1, 2, 2]>,
1115   //
1116   // VST4ln
1117   InstrItinData<IIC_VST4ln,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1118                                InstrStage<1, [A9_MUX0], 0>,
1119                                InstrStage<1, [A9_DRegsN],   0, Required>,
1120                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1121                                InstrStage<3, [A9_NPipe], 1>,
1122                                InstrStage<3, [A9_LSUnit]>],
1123                               [1, 1, 1, 1, 2, 2]>,
1124   //
1125   // VST4lnu
1126   InstrItinData<IIC_VST4lnu,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1127                                InstrStage<1, [A9_MUX0], 0>,
1128                                InstrStage<1, [A9_DRegsN],   0, Required>,
1129                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1130                                InstrStage<3, [A9_NPipe], 1>,
1131                                InstrStage<3, [A9_LSUnit]>],
1132                               [2, 1, 1, 1, 1, 1, 2, 2]>,
1133
1134   //
1135   // Double-register Integer Unary
1136   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1137                                InstrStage<1, [A9_MUX0], 0>,
1138                                InstrStage<1, [A9_DRegsN],   0, Required>,
1139                                // Extra latency cycles since wbck is 6 cycles
1140                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1141                                InstrStage<1, [A9_NPipe]>],
1142                               [4, 2]>,
1143   //
1144   // Quad-register Integer Unary
1145   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1146                                InstrStage<1, [A9_MUX0], 0>,
1147                                InstrStage<1, [A9_DRegsN],   0, Required>,
1148                                // Extra latency cycles since wbck is 6 cycles
1149                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1150                                InstrStage<1, [A9_NPipe]>],
1151                               [4, 2]>,
1152   //
1153   // Double-register Integer Q-Unary
1154   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1155                                InstrStage<1, [A9_MUX0], 0>,
1156                                InstrStage<1, [A9_DRegsN],   0, Required>,
1157                                // Extra latency cycles since wbck is 6 cycles
1158                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1159                                InstrStage<1, [A9_NPipe]>],
1160                               [4, 1]>,
1161   //
1162   // Quad-register Integer CountQ-Unary
1163   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1164                                InstrStage<1, [A9_MUX0], 0>,
1165                                InstrStage<1, [A9_DRegsN],   0, Required>,
1166                                // Extra latency cycles since wbck is 6 cycles
1167                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1168                                InstrStage<1, [A9_NPipe]>],
1169                               [4, 1]>,
1170   //
1171   // Double-register Integer Binary
1172   InstrItinData<IIC_VBINiD,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1173                                InstrStage<1, [A9_MUX0], 0>,
1174                                InstrStage<1, [A9_DRegsN],   0, Required>,
1175                                // Extra latency cycles since wbck is 6 cycles
1176                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1177                                InstrStage<1, [A9_NPipe]>],
1178                               [3, 2, 2]>,
1179   //
1180   // Quad-register Integer Binary
1181   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1182                                InstrStage<1, [A9_MUX0], 0>,
1183                                InstrStage<1, [A9_DRegsN],   0, Required>,
1184                                // Extra latency cycles since wbck is 6 cycles
1185                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1186                                InstrStage<1, [A9_NPipe]>],
1187                               [3, 2, 2]>,
1188   //
1189   // Double-register Integer Subtract
1190   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1191                                InstrStage<1, [A9_MUX0], 0>,
1192                                InstrStage<1, [A9_DRegsN],   0, Required>,
1193                                // Extra latency cycles since wbck is 6 cycles
1194                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1195                                InstrStage<1, [A9_NPipe]>],
1196                               [3, 2, 1]>,
1197   //
1198   // Quad-register Integer Subtract
1199   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1200                                InstrStage<1, [A9_MUX0], 0>,
1201                                InstrStage<1, [A9_DRegsN],   0, Required>,
1202                                // Extra latency cycles since wbck is 6 cycles
1203                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1204                                InstrStage<1, [A9_NPipe]>],
1205                               [3, 2, 1]>,
1206   //
1207   // Double-register Integer Shift
1208   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1209                                InstrStage<1, [A9_MUX0], 0>,
1210                                InstrStage<1, [A9_DRegsN],   0, Required>,
1211                                // Extra latency cycles since wbck is 6 cycles
1212                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1213                                InstrStage<1, [A9_NPipe]>],
1214                               [3, 1, 1]>,
1215   //
1216   // Quad-register Integer Shift
1217   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1218                                InstrStage<1, [A9_MUX0], 0>,
1219                                InstrStage<1, [A9_DRegsN],   0, Required>,
1220                                // Extra latency cycles since wbck is 6 cycles
1221                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1222                                InstrStage<1, [A9_NPipe]>],
1223                               [3, 1, 1]>,
1224   //
1225   // Double-register Integer Shift (4 cycle)
1226   InstrItinData<IIC_VSHLi4D,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1227                                InstrStage<1, [A9_MUX0], 0>,
1228                                InstrStage<1, [A9_DRegsN],   0, Required>,
1229                                // Extra latency cycles since wbck is 6 cycles
1230                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1231                                InstrStage<1, [A9_NPipe]>],
1232                               [4, 1, 1]>,
1233   //
1234   // Quad-register Integer Shift (4 cycle)
1235   InstrItinData<IIC_VSHLi4Q,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1236                                InstrStage<1, [A9_MUX0], 0>,
1237                                InstrStage<1, [A9_DRegsN],   0, Required>,
1238                                // Extra latency cycles since wbck is 6 cycles
1239                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1240                                InstrStage<1, [A9_NPipe]>],
1241                               [4, 1, 1]>,
1242   //
1243   // Double-register Integer Binary (4 cycle)
1244   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1245                                InstrStage<1, [A9_MUX0], 0>,
1246                                InstrStage<1, [A9_DRegsN],   0, Required>,
1247                                // Extra latency cycles since wbck is 6 cycles
1248                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1249                                InstrStage<1, [A9_NPipe]>],
1250                               [4, 2, 2]>,
1251   //
1252   // Quad-register Integer Binary (4 cycle)
1253   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1254                                InstrStage<1, [A9_MUX0], 0>,
1255                                InstrStage<1, [A9_DRegsN],   0, Required>,
1256                                // Extra latency cycles since wbck is 6 cycles
1257                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1258                                InstrStage<1, [A9_NPipe]>],
1259                               [4, 2, 2]>,
1260   //
1261   // Double-register Integer Subtract (4 cycle)
1262   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1263                                InstrStage<1, [A9_MUX0], 0>,
1264                                InstrStage<1, [A9_DRegsN],   0, Required>,
1265                                // Extra latency cycles since wbck is 6 cycles
1266                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1267                                InstrStage<1, [A9_NPipe]>],
1268                               [4, 2, 1]>,
1269   //
1270   // Quad-register Integer Subtract (4 cycle)
1271   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1272                                InstrStage<1, [A9_MUX0], 0>,
1273                                InstrStage<1, [A9_DRegsN],   0, Required>,
1274                                // Extra latency cycles since wbck is 6 cycles
1275                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1276                                InstrStage<1, [A9_NPipe]>],
1277                               [4, 2, 1]>,
1278
1279   //
1280   // Double-register Integer Count
1281   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1282                                InstrStage<1, [A9_MUX0], 0>,
1283                                InstrStage<1, [A9_DRegsN],   0, Required>,
1284                                // Extra latency cycles since wbck is 6 cycles
1285                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1286                                InstrStage<1, [A9_NPipe]>],
1287                               [3, 2, 2]>,
1288   //
1289   // Quad-register Integer Count
1290   // Result written in N3, but that is relative to the last cycle of multicycle,
1291   // so we use 4 for those cases
1292   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1293                                InstrStage<1, [A9_MUX0], 0>,
1294                                InstrStage<1, [A9_DRegsN],   0, Required>,
1295                                // Extra latency cycles since wbck is 7 cycles
1296                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1297                                InstrStage<2, [A9_NPipe]>],
1298                               [4, 2, 2]>,
1299   //
1300   // Double-register Absolute Difference and Accumulate
1301   InstrItinData<IIC_VABAD,    [InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1302                                InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1303                                InstrStage<1, [A9_MUX0], 0>,
1304                                InstrStage<1, [A9_DRegsN],   0, Required>,
1305                                // Extra latency cycles since wbck is 6 cycles
1306                                InstrStage<1, [A9_NPipe]>],
1307                               [6, 3, 2, 1]>,
1308   //
1309   // Quad-register Absolute Difference and Accumulate
1310   InstrItinData<IIC_VABAQ,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1311                                InstrStage<1, [A9_MUX0], 0>,
1312                                InstrStage<1, [A9_DRegsN],   0, Required>,
1313                                // Extra latency cycles since wbck is 6 cycles
1314                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1315                                InstrStage<2, [A9_NPipe]>],
1316                               [6, 3, 2, 1]>,
1317   //
1318   // Double-register Integer Pair Add Long
1319   InstrItinData<IIC_VPALiD,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1320                                InstrStage<1, [A9_MUX0], 0>,
1321                                InstrStage<1, [A9_DRegsN],   0, Required>,
1322                                // Extra latency cycles since wbck is 6 cycles
1323                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1324                                InstrStage<1, [A9_NPipe]>],
1325                               [6, 3, 1]>,
1326   //
1327   // Quad-register Integer Pair Add Long
1328   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1329                                InstrStage<1, [A9_MUX0], 0>,
1330                                InstrStage<1, [A9_DRegsN],   0, Required>,
1331                                // Extra latency cycles since wbck is 6 cycles
1332                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1333                                InstrStage<2, [A9_NPipe]>],
1334                               [6, 3, 1]>,
1335
1336   //
1337   // Double-register Integer Multiply (.8, .16)
1338   InstrItinData<IIC_VMULi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1339                                InstrStage<1, [A9_MUX0], 0>,
1340                                InstrStage<1, [A9_DRegsN],   0, Required>,
1341                                // Extra latency cycles since wbck is 6 cycles
1342                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1343                                InstrStage<1, [A9_NPipe]>],
1344                               [6, 2, 2]>,
1345   //
1346   // Quad-register Integer Multiply (.8, .16)
1347   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1348                                InstrStage<1, [A9_MUX0], 0>,
1349                                InstrStage<1, [A9_DRegsN],   0, Required>,
1350                                // Extra latency cycles since wbck is 7 cycles
1351                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1352                                InstrStage<2, [A9_NPipe]>],
1353                               [7, 2, 2]>,
1354
1355   //
1356   // Double-register Integer Multiply (.32)
1357   InstrItinData<IIC_VMULi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1358                                InstrStage<1, [A9_MUX0], 0>,
1359                                InstrStage<1, [A9_DRegsN],   0, Required>,
1360                                // Extra latency cycles since wbck is 7 cycles
1361                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1362                                InstrStage<2, [A9_NPipe]>],
1363                               [7, 2, 1]>,
1364   //
1365   // Quad-register Integer Multiply (.32)
1366   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1367                                InstrStage<1, [A9_MUX0], 0>,
1368                                InstrStage<1, [A9_DRegsN],   0, Required>,
1369                                // Extra latency cycles since wbck is 9 cycles
1370                                InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
1371                                InstrStage<4, [A9_NPipe]>],
1372                               [9, 2, 1]>,
1373   //
1374   // Double-register Integer Multiply-Accumulate (.8, .16)
1375   InstrItinData<IIC_VMACi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1376                                InstrStage<1, [A9_MUX0], 0>,
1377                                InstrStage<1, [A9_DRegsN],   0, Required>,
1378                                // Extra latency cycles since wbck is 6 cycles
1379                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1380                                InstrStage<1, [A9_NPipe]>],
1381                               [6, 3, 2, 2]>,
1382   //
1383   // Double-register Integer Multiply-Accumulate (.32)
1384   InstrItinData<IIC_VMACi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1385                                InstrStage<1, [A9_MUX0], 0>,
1386                                InstrStage<1, [A9_DRegsN],   0, Required>,
1387                                // Extra latency cycles since wbck is 7 cycles
1388                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1389                                InstrStage<2, [A9_NPipe]>],
1390                               [7, 3, 2, 1]>,
1391   //
1392   // Quad-register Integer Multiply-Accumulate (.8, .16)
1393   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1394                                InstrStage<1, [A9_MUX0], 0>,
1395                                InstrStage<1, [A9_DRegsN],   0, Required>,
1396                                // Extra latency cycles since wbck is 7 cycles
1397                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1398                                InstrStage<2, [A9_NPipe]>],
1399                               [7, 3, 2, 2]>,
1400   //
1401   // Quad-register Integer Multiply-Accumulate (.32)
1402   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1403                                InstrStage<1, [A9_MUX0], 0>,
1404                                InstrStage<1, [A9_DRegsN],   0, Required>,
1405                                // Extra latency cycles since wbck is 9 cycles
1406                                InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
1407                                InstrStage<4, [A9_NPipe]>],
1408                               [9, 3, 2, 1]>,
1409
1410   //
1411   // Move
1412   InstrItinData<IIC_VMOV,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1413                                InstrStage<1, [A9_MUX0], 0>,
1414                                InstrStage<1, [A9_DRegsN],   0, Required>,
1415                                InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1416                                InstrStage<1, [A9_NPipe]>],
1417                               [1,1]>,
1418   //
1419   // Move Immediate
1420   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1421                                InstrStage<1, [A9_MUX0], 0>,
1422                                InstrStage<1, [A9_DRegsN],   0, Required>,
1423                                // Extra latency cycles since wbck is 6 cycles
1424                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1425                                InstrStage<1, [A9_NPipe]>],
1426                               [3]>,
1427   //
1428   // Double-register Permute Move
1429   InstrItinData<IIC_VMOVD,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1430                                InstrStage<1, [A9_MUX0], 0>,
1431                                InstrStage<1, [A9_DRegsN],   0, Required>,
1432                                // Extra latency cycles since wbck is 6 cycles
1433                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1434                                InstrStage<1, [A9_NPipe]>],
1435                               [2, 1]>,
1436   //
1437   // Quad-register Permute Move
1438   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1439                                InstrStage<1, [A9_MUX0], 0>,
1440                                InstrStage<1, [A9_DRegsN],   0, Required>,
1441                                // Extra latency cycles since wbck is 6 cycles
1442                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1443                                InstrStage<1, [A9_NPipe]>],
1444                               [2, 1]>,
1445   //
1446   // Integer to Single-precision Move
1447   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1448                                InstrStage<1, [A9_MUX0], 0>,
1449                                InstrStage<1, [A9_DRegsN],   0, Required>,
1450                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1451                                InstrStage<1, [A9_NPipe]>],
1452                               [1, 1]>,
1453   //
1454   // Integer to Double-precision Move
1455   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1456                                InstrStage<1, [A9_MUX0], 0>,
1457                                InstrStage<1, [A9_DRegsN],   0, Required>,
1458                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1459                                InstrStage<1, [A9_NPipe]>],
1460                               [1, 1, 1]>,
1461   //
1462   // Single-precision to Integer Move
1463   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1464                                InstrStage<1, [A9_MUX0], 0>,
1465                                InstrStage<1, [A9_DRegsN],   0, Required>,
1466                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1467                                InstrStage<1, [A9_NPipe]>],
1468                               [2, 1]>,
1469   //
1470   // Double-precision to Integer Move
1471   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1472                                InstrStage<1, [A9_MUX0], 0>,
1473                                InstrStage<1, [A9_DRegsN],   0, Required>,
1474                                InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1475                                InstrStage<1, [A9_NPipe]>],
1476                               [2, 2, 1]>,
1477   //
1478   // Integer to Lane Move
1479   InstrItinData<IIC_VMOVISL , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1480                                InstrStage<1, [A9_MUX0], 0>,
1481                                InstrStage<1, [A9_DRegsN],   0, Required>,
1482                                InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
1483                                InstrStage<2, [A9_NPipe]>],
1484                               [3, 1, 1]>,
1485
1486   //
1487   // Vector narrow move
1488   InstrItinData<IIC_VMOVN,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1489                                InstrStage<1, [A9_MUX0], 0>,
1490                                InstrStage<1, [A9_DRegsN],   0, Required>,
1491                                // Extra latency cycles since wbck is 6 cycles
1492                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1493                                InstrStage<1, [A9_NPipe]>],
1494                               [3, 1]>,
1495   //
1496   // Double-register FP Unary
1497   InstrItinData<IIC_VUNAD,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1498                                InstrStage<1, [A9_MUX0], 0>,
1499                                InstrStage<1, [A9_DRegsN],   0, Required>,
1500                                // Extra latency cycles since wbck is 6 cycles
1501                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1502                                InstrStage<1, [A9_NPipe]>],
1503                               [5, 2]>,
1504   //
1505   // Quad-register FP Unary
1506   // Result written in N5, but that is relative to the last cycle of multicycle,
1507   // so we use 6 for those cases
1508   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1509                                InstrStage<1, [A9_MUX0], 0>,
1510                                InstrStage<1, [A9_DRegsN],   0, Required>,
1511                                // Extra latency cycles since wbck is 7 cycles
1512                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1513                                InstrStage<2, [A9_NPipe]>],
1514                               [6, 2]>,
1515   //
1516   // Double-register FP Binary
1517   // FIXME: We're using this itin for many instructions and [2, 2] here is too
1518   // optimistic.
1519   InstrItinData<IIC_VBIND,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1520                                InstrStage<1, [A9_MUX0], 0>,
1521                                InstrStage<1, [A9_DRegsN],   0, Required>,
1522                                // Extra latency cycles since wbck is 6 cycles
1523                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1524                                InstrStage<1, [A9_NPipe]>],
1525                               [5, 2, 2]>,
1526
1527   //
1528   // VPADD, etc.
1529   InstrItinData<IIC_VPBIND,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1530                                InstrStage<1, [A9_MUX0], 0>,
1531                                InstrStage<1, [A9_DRegsN],   0, Required>,
1532                                // Extra latency cycles since wbck is 6 cycles
1533                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1534                                InstrStage<1, [A9_NPipe]>],
1535                               [5, 1, 1]>,
1536   //
1537   // Double-register FP VMUL
1538   InstrItinData<IIC_VFMULD,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1539                                InstrStage<1, [A9_MUX0], 0>,
1540                                InstrStage<1, [A9_DRegsN],   0, Required>,
1541                                // Extra latency cycles since wbck is 6 cycles
1542                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1543                                InstrStage<1, [A9_NPipe]>],
1544                               [5, 2, 1]>,
1545   //
1546   // Quad-register FP Binary
1547   // Result written in N5, but that is relative to the last cycle of multicycle,
1548   // so we use 6 for those cases
1549   // FIXME: We're using this itin for many instructions and [2, 2] here is too
1550   // optimistic.
1551   InstrItinData<IIC_VBINQ,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1552                                InstrStage<1, [A9_MUX0], 0>,
1553                                InstrStage<1, [A9_DRegsN],   0, Required>,
1554                                // Extra latency cycles since wbck is 7 cycles
1555                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1556                                InstrStage<2, [A9_NPipe]>],
1557                               [6, 2, 2]>,
1558   //
1559   // Quad-register FP VMUL
1560   InstrItinData<IIC_VFMULQ,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1561                                InstrStage<1, [A9_MUX0], 0>,
1562                                InstrStage<1, [A9_DRegsN],   0, Required>,
1563                                // Extra latency cycles since wbck is 7 cycles
1564                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1565                                InstrStage<1, [A9_NPipe]>],
1566                               [6, 2, 1]>,
1567   //
1568   // Double-register FP Multiple-Accumulate
1569   InstrItinData<IIC_VMACD,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1570                                InstrStage<1, [A9_MUX0], 0>,
1571                                InstrStage<1, [A9_DRegsN],   0, Required>,
1572                                // Extra latency cycles since wbck is 7 cycles
1573                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1574                                InstrStage<2, [A9_NPipe]>],
1575                               [6, 3, 2, 1]>,
1576   //
1577   // Quad-register FP Multiple-Accumulate
1578   // Result written in N9, but that is relative to the last cycle of multicycle,
1579   // so we use 10 for those cases
1580   InstrItinData<IIC_VMACQ,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1581                                InstrStage<1, [A9_MUX0], 0>,
1582                                InstrStage<1, [A9_DRegsN],   0, Required>,
1583                                // Extra latency cycles since wbck is 9 cycles
1584                                InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
1585                                InstrStage<4, [A9_NPipe]>],
1586                               [8, 4, 2, 1]>,
1587   //
1588   // Double-register Reciprical Step
1589   InstrItinData<IIC_VRECSD,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1590                                InstrStage<1, [A9_MUX0], 0>,
1591                                InstrStage<1, [A9_DRegsN],   0, Required>,
1592                                // Extra latency cycles since wbck is 10 cycles
1593                                InstrStage<11, [A9_DRegsVFP], 0, Reserved>,
1594                                InstrStage<1, [A9_NPipe]>],
1595                               [9, 2, 2]>,
1596   //
1597   // Quad-register Reciprical Step
1598   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1599                                InstrStage<1, [A9_MUX0], 0>,
1600                                InstrStage<1, [A9_DRegsN],   0, Required>,
1601                                // Extra latency cycles since wbck is 11 cycles
1602                                InstrStage<12, [A9_DRegsVFP], 0, Reserved>,
1603                                InstrStage<2, [A9_NPipe]>],
1604                               [10, 2, 2]>,
1605   //
1606   // Double-register Permute
1607   InstrItinData<IIC_VPERMD,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1608                                InstrStage<1, [A9_MUX0], 0>,
1609                                InstrStage<1, [A9_DRegsN],   0, Required>,
1610                                // Extra latency cycles since wbck is 6 cycles
1611                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1612                                InstrStage<1, [A9_NPipe]>],
1613                               [2, 2, 1, 1]>,
1614   //
1615   // Quad-register Permute
1616   // Result written in N2, but that is relative to the last cycle of multicycle,
1617   // so we use 3 for those cases
1618   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1619                                InstrStage<1, [A9_MUX0], 0>,
1620                                InstrStage<1, [A9_DRegsN],   0, Required>,
1621                                // Extra latency cycles since wbck is 7 cycles
1622                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1623                                InstrStage<2, [A9_NPipe]>],
1624                               [3, 3, 1, 1]>,
1625   //
1626   // Quad-register Permute (3 cycle issue)
1627   // Result written in N2, but that is relative to the last cycle of multicycle,
1628   // so we use 4 for those cases
1629   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1630                                InstrStage<1, [A9_MUX0], 0>,
1631                                InstrStage<1, [A9_DRegsN],   0, Required>,
1632                                // Extra latency cycles since wbck is 8 cycles
1633                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1634                                InstrStage<3, [A9_NPipe]>],
1635                               [4, 4, 1, 1]>,
1636
1637   //
1638   // Double-register VEXT
1639   InstrItinData<IIC_VEXTD,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1640                                InstrStage<1, [A9_MUX0], 0>,
1641                                InstrStage<1, [A9_DRegsN],   0, Required>,
1642                                // Extra latency cycles since wbck is 6 cycles
1643                                InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1644                                InstrStage<1, [A9_NPipe]>],
1645                               [2, 1, 1]>,
1646   //
1647   // Quad-register VEXT
1648   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1649                                InstrStage<1, [A9_MUX0], 0>,
1650                                InstrStage<1, [A9_DRegsN],   0, Required>,
1651                                // Extra latency cycles since wbck is 7 cycles
1652                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1653                                InstrStage<2, [A9_NPipe]>],
1654                               [3, 1, 2]>,
1655   //
1656   // VTB
1657   InstrItinData<IIC_VTB1,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1658                                InstrStage<1, [A9_MUX0], 0>,
1659                                InstrStage<1, [A9_DRegsN],   0, Required>,
1660                                // Extra latency cycles since wbck is 7 cycles
1661                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1662                                InstrStage<2, [A9_NPipe]>],
1663                               [3, 2, 1]>,
1664   InstrItinData<IIC_VTB2,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1665                                InstrStage<1, [A9_MUX0], 0>,
1666                                InstrStage<2, [A9_DRegsN],   0, Required>,
1667                                // Extra latency cycles since wbck is 7 cycles
1668                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1669                                InstrStage<2, [A9_NPipe]>],
1670                               [3, 2, 2, 1]>,
1671   InstrItinData<IIC_VTB3,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1672                                InstrStage<1, [A9_MUX0], 0>,
1673                                InstrStage<2, [A9_DRegsN],   0, Required>,
1674                                // Extra latency cycles since wbck is 8 cycles
1675                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1676                                InstrStage<3, [A9_NPipe]>],
1677                               [4, 2, 2, 3, 1]>,
1678   InstrItinData<IIC_VTB4,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1679                                InstrStage<1, [A9_MUX0], 0>,
1680                                InstrStage<1, [A9_DRegsN],   0, Required>,
1681                                // Extra latency cycles since wbck is 8 cycles
1682                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1683                                InstrStage<3, [A9_NPipe]>],
1684                               [4, 2, 2, 3, 3, 1]>,
1685   //
1686   // VTBX
1687   InstrItinData<IIC_VTBX1,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1688                                InstrStage<1, [A9_MUX0], 0>,
1689                                InstrStage<1, [A9_DRegsN],   0, Required>,
1690                                // Extra latency cycles since wbck is 7 cycles
1691                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1692                                InstrStage<2, [A9_NPipe]>],
1693                               [3, 1, 2, 1]>,
1694   InstrItinData<IIC_VTBX2,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1695                                InstrStage<1, [A9_MUX0], 0>,
1696                                InstrStage<1, [A9_DRegsN],   0, Required>,
1697                                // Extra latency cycles since wbck is 7 cycles
1698                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1699                                InstrStage<2, [A9_NPipe]>],
1700                               [3, 1, 2, 2, 1]>,
1701   InstrItinData<IIC_VTBX3,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1702                                InstrStage<1, [A9_MUX0], 0>,
1703                                InstrStage<1, [A9_DRegsN],   0, Required>,
1704                                // Extra latency cycles since wbck is 8 cycles
1705                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1706                                InstrStage<3, [A9_NPipe]>],
1707                               [4, 1, 2, 2, 3, 1]>,
1708   InstrItinData<IIC_VTBX4,    [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1709                                InstrStage<1, [A9_MUX0], 0>,
1710                                InstrStage<1, [A9_DRegsN],   0, Required>,
1711                                // Extra latency cycles since wbck is 8 cycles
1712                                InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1713                                InstrStage<2, [A9_NPipe]>],
1714                               [4, 1, 2, 2, 3, 3, 1]>
1715 ]>;