1 //===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM v6 processors.
12 //===----------------------------------------------------------------------===//
14 // TODO: this should model an ARM11
15 // Single issue pipeline so every itinerary starts with FU_pipe0
16 def V6Itineraries : ProcessorItineraries<[
17 InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>,
18 InstrItinData<IIC_iMPYh , [InstrStage<1, [FU_Pipe0]>]>,
19 InstrItinData<IIC_iMPYw , [InstrStage<1, [FU_Pipe0]>]>,
20 InstrItinData<IIC_iMPYl , [InstrStage<1, [FU_Pipe0]>]>,
21 InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
22 InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>,
23 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
24 InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
25 InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,
26 InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
27 InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>