1 //===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM v7 processors.
12 //===----------------------------------------------------------------------===//
14 // Single issue pipeline so every itinerary starts with FU_Pipe0
15 def V7Itineraries : ProcessorItineraries<[
16 // single-cycle integer ALU
17 InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>,
18 // loads have an extra cycle of latency, but are fully pipelined
19 InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
20 InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
21 // fully-pipelined stores
22 InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>,
23 InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>,
24 // fp ALU is not pipelined
25 InstrItinData<IIC_fpALU , [InstrStage<6, [FU_Pipe0]>]>,
26 // no delay slots, so the latency of a branch is unimportant
27 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>
30 // Dual issue pipeline so every itinerary starts with FU_Pipe0 | FU_Pipe1
31 def CortexA8Itineraries : ProcessorItineraries<[
32 // single-cycle integer ALU
33 InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
34 // loads have an extra cycle of latency, but are fully pipelined
35 InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0]>]>,
36 InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0]>]>,
37 // fully-pipelined stores
38 InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
39 InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
40 // fp ALU is not pipelined
41 InstrItinData<IIC_fpALU , [InstrStage<6, [FU_Pipe0, FU_Pipe1]>]>,
42 // no delay slots, so the latency of a branch is unimportant
43 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>