1 //===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM v7 processors.
12 //===----------------------------------------------------------------------===//
14 // Dual issue pipeline so every itinerary starts with FU_Pipe0 | FU_Pipe1
15 def CortexA8Itineraries : ProcessorItineraries<[
16 // two fully-pipelined integer ALU pipelines
17 InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
18 // one fully-pipelined integer Multiply pipeline
19 // function units are reserved by the scheduler in reverse alpha order,
20 // so use FU_Pipe0 for the Multiple pipeline
21 InstrItinData<IIC_iMPY , [InstrStage<1, [FU_Pipe0]>]>,
22 // loads have an extra cycle of latency, but are fully pipelined
23 // use FU_Issue to enforce the 1 load/store per cycle limit
24 InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Issue], 0>,
25 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
26 InstrStage<1, [FU_LdSt0]>]>,
27 // fully-pipelined stores
28 // use FU_Issue to enforce the 1 load/store per cycle limit
29 InstrItinData<IIC_iStore , [InstrStage<1, [FU_Issue], 0>,
30 InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
31 // no delay slots, so the latency of a branch is unimportant
32 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
34 // NFP ALU is not pipelined so stall all issues
35 InstrItinData<IIC_fpALU , [InstrStage<7, [FU_Pipe0], 0>,
36 InstrStage<7, [FU_Pipe1], 0>]>,
37 // VFP MPY is not pipelined so stall all issues
38 InstrItinData<IIC_fpMPY , [InstrStage<7, [FU_Pipe0], 0>,
39 InstrStage<7, [FU_Pipe1], 0>]>,
40 // loads have an extra cycle of latency, but are fully pipelined
41 // use FU_Issue to enforce the 1 load/store per cycle limit
42 InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Issue], 0>,
43 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
44 InstrStage<1, [FU_LdSt0]>]>,
45 // use FU_Issue to enforce the 1 load/store per cycle limit
46 InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Issue], 0>,
47 InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>
51 def CortexA9Itineraries : ProcessorItineraries<[
52 InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>,
53 InstrItinData<IIC_iMPY , [InstrStage<1, [FU_Pipe0]>]>,
54 InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
55 InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>,
56 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
57 InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
58 InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,
59 InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
60 InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>