lib/Target/ARM/ARMScheduleV7.td

   1 //===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM v7 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Dual issue pipeline so every itinerary starts with FU_Pipe0 | FU_Pipe1
  15 def CortexA8Itineraries : ProcessorItineraries<[
  16   // two fully-pipelined integer ALU pipelines
  17   InstrItinData<IIC_iALU    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
  18   // integer Multiply pipeline
  19   InstrItinData<IIC_iMPYh   , [InstrStage<1, [FU_Pipe0]>]>,
  20   InstrItinData<IIC_iMPYw   , [InstrStage<1, [FU_Pipe1], 0>,
  21                                InstrStage<2, [FU_Pipe0]>]>,
  22   InstrItinData<IIC_iMPYl   , [InstrStage<2, [FU_Pipe1], 0>,
  23                                InstrStage<3, [FU_Pipe0]>]>,
  24   // loads have an extra cycle of latency, but are fully pipelined
  25   // use FU_Issue to enforce the 1 load/store per cycle limit
  26   InstrItinData<IIC_iLoad   , [InstrStage<1, [FU_Issue], 0>,
  27                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  28                                InstrStage<1, [FU_LdSt0]>]>,
  29   // fully-pipelined stores
  30   // use FU_Issue to enforce the 1 load/store per cycle limit
  31   InstrItinData<IIC_iStore  , [InstrStage<1, [FU_Issue], 0>,
  32                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
  33   // no delay slots, so the latency of a branch is unimportant
  34   InstrItinData<IIC_Br      , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
  35
  36   // NFP ALU is not pipelined so stall all issues
  37   InstrItinData<IIC_fpALU   , [InstrStage<7, [FU_Pipe0], 0>,
  38                                InstrStage<7, [FU_Pipe1], 0>]>,
  39   // VFP MPY is not pipelined so stall all issues
  40   InstrItinData<IIC_fpMPY   , [InstrStage<7, [FU_Pipe0], 0>,
  41                                InstrStage<7, [FU_Pipe1], 0>]>,
  42   // loads have an extra cycle of latency, but are fully pipelined
  43   // use FU_Issue to enforce the 1 load/store per cycle limit
  44   InstrItinData<IIC_fpLoad  , [InstrStage<1, [FU_Issue], 0>,
  45                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  46                                InstrStage<1, [FU_LdSt0]>]>,
  47   // use FU_Issue to enforce the 1 load/store per cycle limit
  48   InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Issue], 0>,
  49                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>
  50 ]>;
  51
  52 // FIXME
  53 def CortexA9Itineraries : ProcessorItineraries<[
  54   InstrItinData<IIC_iALU    , [InstrStage<1, [FU_Pipe0]>]>,
  55   InstrItinData<IIC_iMPYh   , [InstrStage<1, [FU_Pipe0]>]>,
  56   InstrItinData<IIC_iMPYw   , [InstrStage<1, [FU_Pipe0]>]>,
  57   InstrItinData<IIC_iMPYl   , [InstrStage<1, [FU_Pipe0]>]>,
  58   InstrItinData<IIC_iLoad   , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
  59   InstrItinData<IIC_iStore  , [InstrStage<1, [FU_Pipe0]>]>,
  60   InstrItinData<IIC_Br      , [InstrStage<1, [FU_Pipe0]>]>,
  61   InstrItinData<IIC_fpALU   , [InstrStage<1, [FU_Pipe0]>]>,
  62   InstrItinData<IIC_fpMPY   , [InstrStage<1, [FU_Pipe0]>]>,
  63   InstrItinData<IIC_fpLoad  , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
  64   InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
  65 ]>;