1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "llvm/GlobalValue.h"
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "llvm/Support/CommandLine.h"
21 #define GET_SUBTARGETINFO_TARGET_DESC
22 #define GET_SUBTARGETINFO_CTOR
23 #include "ARMGenSubtargetInfo.inc"
28 ReserveR9("arm-reserve-r9", cl::Hidden,
29 cl::desc("Reserve R9, making it unavailable as GPR"));
32 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
35 StrictAlign("arm-strict-align", cl::Hidden,
36 cl::desc("Disallow all unaligned memory accesses"));
38 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
39 const std::string &FS)
40 : ARMGenSubtargetInfo(TT, CPU, FS)
41 , ARMProcFamily(Others)
52 , UseNEONForSinglePrecisionFP(false)
54 , HasVMLxForwarding(false)
60 , PostRAScheduler(false)
61 , IsR9Reserved(ReserveR9)
63 , SupportsTailCall(false)
66 , HasHardwareDivide(false)
67 , HasT2ExtractPack(false)
68 , HasDataBarrier(false)
69 , Pref32BitThumb(false)
70 , AvoidCPSRPartialUpdate(false)
72 , HasMPExtension(false)
74 , AllowsUnalignedMem(false)
79 , TargetABI(ARM_ABI_APCS) {
80 // Determine default and user specified characteristics
81 if (CPUString.empty())
82 CPUString = "generic";
84 // Insert the architecture feature derived from the target triple into the
85 // feature string. This is important for setting features that are implied
86 // based on the architecture version.
87 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString);
90 ArchFS = ArchFS + "," + FS;
94 ParseSubtargetFeatures(CPUString, ArchFS);
96 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
97 // ARM version or CPU and then remove this.
98 if (!HasV6T2Ops && hasThumb2())
99 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
101 // Keep a pointer to static instruction cost data for the specified CPU.
102 SchedModel = getSchedModelForCPU(CPUString);
104 // Initialize scheduling itinerary for the specified CPU.
105 InstrItins = getInstrItineraryForCPU(CPUString);
107 if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass()))
108 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
109 // Darwin-EABI conforms to AACPS but not the rest of EABI.
110 TargetABI = ARM_ABI_AAPCS;
116 UseMovt = hasV6T2Ops();
118 IsR9Reserved = ReserveR9 | !HasV6Ops;
119 UseMovt = DarwinUseMOVT && hasV6T2Ops();
120 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
123 if (!isThumb() || hasThumb2())
124 PostRAScheduler = true;
126 // v6+ may or may not support unaligned mem access depending on the system
128 if (!StrictAlign && hasV6Ops() && isTargetDarwin())
129 AllowsUnalignedMem = true;
132 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
134 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
135 Reloc::Model RelocM) const {
136 if (RelocM == Reloc::Static)
139 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
141 bool isDecl = GV->hasAvailableExternallyLinkage();
142 if (GV->isDeclaration() && !GV->isMaterializable())
145 if (!isTargetDarwin()) {
146 // Extra load is needed for all externally visible.
147 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
151 if (RelocM == Reloc::PIC_) {
152 // If this is a strong reference to a definition, it is definitely not
154 if (!isDecl && !GV->isWeakForLinker())
157 // Unless we have a symbol with hidden visibility, we have to go through a
158 // normal $non_lazy_ptr stub because this symbol might be resolved late.
159 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
162 // If symbol visibility is hidden, we have a stub for common symbol
163 // references and external declarations.
164 if (isDecl || GV->hasCommonLinkage())
165 // Hidden $non_lazy_ptr reference.
170 // If this is a strong reference to a definition, it is definitely not
172 if (!isDecl && !GV->isWeakForLinker())
175 // Unless we have a symbol with hidden visibility, we have to go through a
176 // normal $non_lazy_ptr stub because this symbol might be resolved late.
177 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
185 unsigned ARMSubtarget::getMispredictionPenalty() const {
186 return SchedModel->MispredictPenalty;
189 bool ARMSubtarget::enablePostRAScheduler(
190 CodeGenOpt::Level OptLevel,
191 TargetSubtargetInfo::AntiDepBreakMode& Mode,
192 RegClassVector& CriticalPathRCs) const {
193 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
194 CriticalPathRCs.clear();
195 CriticalPathRCs.push_back(&ARM::GPRRegClass);
196 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;