1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMSelectionDAGInfo.h"
19 #include "ARMSubtarget.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "Thumb1FrameLowering.h"
22 #include "Thumb1InstrInfo.h"
23 #include "Thumb2InstrInfo.h"
24 #include "llvm/IR/Attributes.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalValue.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #define DEBUG_TYPE "arm-subtarget"
37 #define GET_SUBTARGETINFO_TARGET_DESC
38 #define GET_SUBTARGETINFO_CTOR
39 #include "ARMGenSubtargetInfo.inc"
42 ReserveR9("arm-reserve-r9", cl::Hidden,
43 cl::desc("Reserve R9, making it unavailable as GPR"));
46 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
49 UseFusedMulOps("arm-use-mulops",
50 cl::init(true), cl::Hidden);
60 static cl::opt<AlignMode>
61 Align(cl::desc("Load/store alignment support"),
62 cl::Hidden, cl::init(DefaultAlign),
64 clEnumValN(DefaultAlign, "arm-default-align",
65 "Generate unaligned accesses only on hardware/OS "
66 "combinations that are known to support them"),
67 clEnumValN(StrictAlign, "arm-strict-align",
68 "Disallow all unaligned memory accesses"),
69 clEnumValN(NoStrictAlign, "arm-no-strict-align",
70 "Allow unaligned memory accesses"),
79 static cl::opt<ITMode>
80 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
82 cl::values(clEnumValN(DefaultIT, "arm-default-it",
83 "Generate IT block based on arch"),
84 clEnumValN(RestrictedIT, "arm-restrict-it",
85 "Disallow deprecated IT based on ARMv8"),
86 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
87 "Allow IT blocks based on ARMv7"),
90 static std::string computeDataLayout(ARMSubtarget &ST) {
100 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
102 // Pointers are 32 bits and aligned to 32 bits.
105 // ABIs other than APCS have 64 bit integers with natural alignment.
106 if (!ST.isAPCS_ABI())
109 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
110 // bits, others to 64 bits. We always try to align to 64 bits.
114 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
115 // to 64. We always ty to give them natural alignment.
117 Ret += "-v64:32:64-v128:32:128";
119 Ret += "-v128:64:128";
121 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
122 // particular hardware support on 32-bit ARM).
125 // Integer registers are 32 bits.
128 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
129 // aligned everywhere else.
130 if (ST.isTargetNaCl())
132 else if (ST.isAAPCS_ABI())
140 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
141 /// so that we can use initializer lists for subtarget initialization.
142 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
144 initializeEnvironment();
145 initSubtargetFeatures(CPU, FS);
149 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
150 const std::string &FS, const TargetMachine &TM,
152 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
153 ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
154 TargetTriple(TT), Options(TM.Options), TargetABI(ARM_ABI_UNKNOWN),
155 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
157 InstrInfo(isThumb1Only()
158 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
160 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
161 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
163 FrameLowering(!isThumb1Only()
164 ? new ARMFrameLowering(*this)
165 : (ARMFrameLowering *)new Thumb1FrameLowering(*this)) {}
167 void ARMSubtarget::initializeEnvironment() {
181 UseNEONForSinglePrecisionFP = false;
182 UseMulOps = UseFusedMulOps;
184 HasVMLxForwarding = false;
189 IsR9Reserved = ReserveR9;
191 SupportsTailCall = false;
194 HasHardwareDivide = false;
195 HasHardwareDivideInARM = false;
196 HasT2ExtractPack = false;
197 HasDataBarrier = false;
198 Pref32BitThumb = false;
199 AvoidCPSRPartialUpdate = false;
200 AvoidMOVsShifterOperand = false;
202 HasMPExtension = false;
203 HasVirtualization = false;
206 HasTrustZone = false;
209 HasZeroCycleZeroing = false;
210 AllowsUnalignedMem = false;
213 UnsafeFPMath = false;
216 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
217 if (CPUString.empty()) {
218 if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s"))
219 // Default to the Swift CPU when targeting armv7s/thumbv7s.
222 CPUString = "generic";
225 // Insert the architecture feature derived from the target triple into the
226 // feature string. This is important for setting features that are implied
227 // based on the architecture version.
229 ARM_MC::ParseARMTriple(TargetTriple.getTriple(), CPUString);
232 ArchFS = ArchFS + "," + FS.str();
236 ParseSubtargetFeatures(CPUString, ArchFS);
238 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
239 // Assert this for now to make the change obvious.
240 assert(hasV6T2Ops() || !hasThumb2());
242 // Keep a pointer to static instruction cost data for the specified CPU.
243 SchedModel = getSchedModelForCPU(CPUString);
245 // Initialize scheduling itinerary for the specified CPU.
246 InstrItins = getInstrItineraryForCPU(CPUString);
248 if (TargetABI == ARM_ABI_UNKNOWN) {
249 // FIXME: This is duplicated code from the front end and should be unified.
250 if (TargetTriple.isOSBinFormatMachO()) {
251 if (TargetTriple.getEnvironment() == llvm::Triple::EABI ||
252 (TargetTriple.getOS() == llvm::Triple::UnknownOS &&
253 TargetTriple.getObjectFormat() == llvm::Triple::MachO) ||
254 CPU.startswith("cortex-m")) {
255 TargetABI = ARM_ABI_AAPCS;
257 TargetABI = ARM_ABI_APCS;
259 } else if (TargetTriple.isOSWindows()) {
260 // FIXME: this is invalid for WindowsCE
261 TargetABI = ARM_ABI_AAPCS;
263 // Select the default based on the platform.
264 switch (TargetTriple.getEnvironment()) {
265 case llvm::Triple::Android:
266 case llvm::Triple::GNUEABI:
267 case llvm::Triple::GNUEABIHF:
268 case llvm::Triple::EABIHF:
269 case llvm::Triple::EABI:
270 TargetABI = ARM_ABI_AAPCS;
272 case llvm::Triple::GNU:
273 TargetABI = ARM_ABI_APCS;
276 if (TargetTriple.getOS() == llvm::Triple::NetBSD)
277 TargetABI = ARM_ABI_APCS;
279 TargetABI = ARM_ABI_AAPCS;
285 // FIXME: this is invalid for WindowsCE
286 if (isTargetWindows())
294 UseMovt = hasV6T2Ops() && ArmUseMOVT;
296 if (isTargetMachO()) {
297 IsR9Reserved = ReserveR9 || !HasV6Ops;
298 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
300 IsR9Reserved = ReserveR9;
301 SupportsTailCall = !isThumb1Only();
304 if (Align == DefaultAlign) {
305 // Assume pre-ARMv6 doesn't support unaligned accesses.
307 // ARMv6 may or may not support unaligned accesses depending on the
308 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
309 // Darwin and NetBSD targets support unaligned accesses, and others don't.
311 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
312 // which raises an alignment fault on unaligned accesses. Linux
313 // defaults this bit to 0 and handles it as a system-wide (not
314 // per-process) setting. It is therefore safe to assume that ARMv7+
315 // Linux targets support unaligned accesses. The same goes for NaCl.
317 // The above behavior is consistent with GCC.
319 (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
320 isTargetNetBSD())) ||
321 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
323 AllowsUnalignedMem = !(Align == StrictAlign);
326 // No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
328 AllowsUnalignedMem = false;
332 RestrictIT = hasV8Ops() ? true : false;
342 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
343 uint64_t Bits = getFeatureBits();
344 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
345 (Options.UnsafeFPMath || isTargetDarwin()))
346 UseNEONForSinglePrecisionFP = true;
349 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
351 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
352 Reloc::Model RelocM) const {
353 if (RelocM == Reloc::Static)
356 bool isDecl = GV->isDeclarationForLinker();
358 if (!isTargetMachO()) {
359 // Extra load is needed for all externally visible.
360 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
364 if (RelocM == Reloc::PIC_) {
365 // If this is a strong reference to a definition, it is definitely not
367 if (!isDecl && !GV->isWeakForLinker())
370 // Unless we have a symbol with hidden visibility, we have to go through a
371 // normal $non_lazy_ptr stub because this symbol might be resolved late.
372 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
375 // If symbol visibility is hidden, we have a stub for common symbol
376 // references and external declarations.
377 if (isDecl || GV->hasCommonLinkage())
378 // Hidden $non_lazy_ptr reference.
383 // If this is a strong reference to a definition, it is definitely not
385 if (!isDecl && !GV->isWeakForLinker())
388 // Unless we have a symbol with hidden visibility, we have to go through a
389 // normal $non_lazy_ptr stub because this symbol might be resolved late.
390 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
398 unsigned ARMSubtarget::getMispredictionPenalty() const {
399 return SchedModel.MispredictPenalty;
402 bool ARMSubtarget::hasSinCos() const {
403 return getTargetTriple().isiOS() && !getTargetTriple().isOSVersionLT(7, 0);
406 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
407 bool ARMSubtarget::enablePostMachineScheduler() const {
408 return (!isThumb() || hasThumb2());
411 bool ARMSubtarget::enableAtomicExpand() const {
412 return hasAnyDataBarrier() && !isThumb1Only();
415 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
416 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
417 // immediates as it is inherently position independent, and may be out of
419 return UseMovt && (isTargetWindows() ||
420 !MF.getFunction()->getAttributes().hasAttribute(
421 AttributeSet::FunctionIndex, Attribute::MinSize));