1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMSelectionDAGInfo.h"
19 #include "ARMSubtarget.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "Thumb1FrameLowering.h"
22 #include "Thumb1InstrInfo.h"
23 #include "Thumb2InstrInfo.h"
24 #include "llvm/IR/Attributes.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalValue.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #define DEBUG_TYPE "arm-subtarget"
37 #define GET_SUBTARGETINFO_TARGET_DESC
38 #define GET_SUBTARGETINFO_CTOR
39 #include "ARMGenSubtargetInfo.inc"
42 ReserveR9("arm-reserve-r9", cl::Hidden,
43 cl::desc("Reserve R9, making it unavailable as GPR"));
46 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
49 UseFusedMulOps("arm-use-mulops",
50 cl::init(true), cl::Hidden);
58 static cl::opt<AlignMode>
59 Align(cl::desc("Load/store alignment support"),
60 cl::Hidden, cl::init(DefaultAlign),
62 clEnumValN(DefaultAlign, "arm-default-align",
63 "Generate unaligned accesses only on hardware/OS "
64 "combinations that are known to support them"),
65 clEnumValN(StrictAlign, "arm-strict-align",
66 "Disallow all unaligned memory accesses"),
67 clEnumValN(NoStrictAlign, "arm-no-strict-align",
68 "Allow unaligned memory accesses"),
77 static cl::opt<ITMode>
78 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
80 cl::values(clEnumValN(DefaultIT, "arm-default-it",
81 "Generate IT block based on arch"),
82 clEnumValN(RestrictedIT, "arm-restrict-it",
83 "Disallow deprecated IT based on ARMv8"),
84 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
85 "Allow IT blocks based on ARMv7"),
88 static std::string computeDataLayout(ARMSubtarget &ST) {
98 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
100 // Pointers are 32 bits and aligned to 32 bits.
103 // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
106 Ret += "-i1:8:32-i8:8:32-i16:16:32";
108 // ABIs other than APCS have 64 bit integers with natural alignment.
109 if (!ST.isAPCS_ABI())
112 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
113 // bits, others to 64 bits. We always try to align to 64 bits.
117 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
118 // to 64. We always ty to give them natural alignment.
120 Ret += "-v64:32:64-v128:32:128";
122 Ret += "-v128:64:128";
124 // On thumb and APCS, only try to align aggregates to 32 bits (the default is
126 if (ST.isThumb() || ST.isAPCS_ABI())
129 // Integer registers are 32 bits.
132 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
133 // aligned everywhere else.
134 if (ST.isTargetNaCl())
136 else if (ST.isAAPCS_ABI())
144 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
145 /// so that we can use initializer lists for subtarget initialization.
146 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
148 initializeEnvironment();
149 resetSubtargetFeatures(CPU, FS);
153 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
154 const std::string &FS, TargetMachine &TM,
155 bool IsLittle, const TargetOptions &Options)
156 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
157 ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
158 TargetTriple(TT), Options(Options), TargetABI(ARM_ABI_UNKNOWN),
159 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
161 InstrInfo(isThumb1Only()
162 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
164 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
165 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
167 FrameLowering(!isThumb1Only()
168 ? new ARMFrameLowering(*this)
169 : (ARMFrameLowering *)new Thumb1FrameLowering(*this)) {}
171 void ARMSubtarget::initializeEnvironment() {
185 UseNEONForSinglePrecisionFP = false;
186 UseMulOps = UseFusedMulOps;
188 HasVMLxForwarding = false;
193 IsR9Reserved = ReserveR9;
195 SupportsTailCall = false;
198 HasHardwareDivide = false;
199 HasHardwareDivideInARM = false;
200 HasT2ExtractPack = false;
201 HasDataBarrier = false;
202 Pref32BitThumb = false;
203 AvoidCPSRPartialUpdate = false;
204 AvoidMOVsShifterOperand = false;
206 HasMPExtension = false;
207 HasVirtualization = false;
210 HasTrustZone = false;
213 HasZeroCycleZeroing = false;
214 AllowsUnalignedMem = false;
217 UnsafeFPMath = false;
220 void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
221 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
222 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
224 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
227 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
229 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
231 initializeEnvironment();
232 resetSubtargetFeatures(CPU, FS);
236 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
237 if (CPUString.empty()) {
238 if (isTargetIOS() && TargetTriple.getArchName().endswith("v7s"))
239 // Default to the Swift CPU when targeting armv7s/thumbv7s.
242 CPUString = "generic";
245 // Insert the architecture feature derived from the target triple into the
246 // feature string. This is important for setting features that are implied
247 // based on the architecture version.
248 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
252 ArchFS = ArchFS + "," + FS.str();
256 ParseSubtargetFeatures(CPUString, ArchFS);
258 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
259 // Assert this for now to make the change obvious.
260 assert(hasV6T2Ops() || !hasThumb2());
262 // Keep a pointer to static instruction cost data for the specified CPU.
263 SchedModel = getSchedModelForCPU(CPUString);
265 // Initialize scheduling itinerary for the specified CPU.
266 InstrItins = getInstrItineraryForCPU(CPUString);
268 if (TargetABI == ARM_ABI_UNKNOWN) {
269 switch (TargetTriple.getEnvironment()) {
270 case Triple::Android:
273 case Triple::GNUEABI:
274 case Triple::GNUEABIHF:
275 TargetABI = ARM_ABI_AAPCS;
278 if ((isTargetIOS() && isMClass()) ||
279 (TargetTriple.isOSBinFormatMachO() &&
280 TargetTriple.getOS() == Triple::UnknownOS))
281 TargetABI = ARM_ABI_AAPCS;
283 TargetABI = ARM_ABI_APCS;
288 // FIXME: this is invalid for WindowsCE
289 if (isTargetWindows()) {
290 TargetABI = ARM_ABI_AAPCS;
299 UseMovt = hasV6T2Ops() && ArmUseMOVT;
301 if (isTargetMachO()) {
302 IsR9Reserved = ReserveR9 | !HasV6Ops;
303 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
305 IsR9Reserved = ReserveR9;
306 SupportsTailCall = !isThumb1Only();
311 // Assume pre-ARMv6 doesn't support unaligned accesses.
313 // ARMv6 may or may not support unaligned accesses depending on the
314 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
315 // Darwin and NetBSD targets support unaligned accesses, and others don't.
317 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
318 // which raises an alignment fault on unaligned accesses. Linux
319 // defaults this bit to 0 and handles it as a system-wide (not
320 // per-process) setting. It is therefore safe to assume that ARMv7+
321 // Linux targets support unaligned accesses. The same goes for NaCl.
323 // The above behavior is consistent with GCC.
325 (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
326 isTargetNetBSD())) ||
327 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
328 // The one exception is cortex-m0, which despite being v6, does not
329 // support unaligned accesses. Rather than make the above boolean
330 // expression even more obtuse, just override the value here.
331 if (isThumb1Only() && isMClass())
332 AllowsUnalignedMem = false;
335 AllowsUnalignedMem = false;
338 AllowsUnalignedMem = true;
344 RestrictIT = hasV8Ops() ? true : false;
354 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
355 uint64_t Bits = getFeatureBits();
356 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
357 (Options.UnsafeFPMath || isTargetDarwin()))
358 UseNEONForSinglePrecisionFP = true;
361 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
363 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
364 Reloc::Model RelocM) const {
365 if (RelocM == Reloc::Static)
368 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
370 bool isDecl = GV->hasAvailableExternallyLinkage();
371 if (GV->isDeclaration() && !GV->isMaterializable())
374 if (!isTargetMachO()) {
375 // Extra load is needed for all externally visible.
376 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
380 if (RelocM == Reloc::PIC_) {
381 // If this is a strong reference to a definition, it is definitely not
383 if (!isDecl && !GV->isWeakForLinker())
386 // Unless we have a symbol with hidden visibility, we have to go through a
387 // normal $non_lazy_ptr stub because this symbol might be resolved late.
388 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
391 // If symbol visibility is hidden, we have a stub for common symbol
392 // references and external declarations.
393 if (isDecl || GV->hasCommonLinkage())
394 // Hidden $non_lazy_ptr reference.
399 // If this is a strong reference to a definition, it is definitely not
401 if (!isDecl && !GV->isWeakForLinker())
404 // Unless we have a symbol with hidden visibility, we have to go through a
405 // normal $non_lazy_ptr stub because this symbol might be resolved late.
406 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
414 unsigned ARMSubtarget::getMispredictionPenalty() const {
415 return SchedModel->MispredictPenalty;
418 bool ARMSubtarget::hasSinCos() const {
419 return getTargetTriple().getOS() == Triple::IOS &&
420 !getTargetTriple().isOSVersionLT(7, 0);
423 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
424 bool ARMSubtarget::enablePostMachineScheduler() const {
425 return (!isThumb() || hasThumb2());
428 bool ARMSubtarget::enableAtomicExpandLoadLinked() const {
429 return hasAnyDataBarrier() && !isThumb1Only();
432 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
433 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
434 // immediates as it is inherently position independent, and may be out of
436 return UseMovt && (isTargetWindows() ||
437 !MF.getFunction()->getAttributes().hasAttribute(
438 AttributeSet::FunctionIndex, Attribute::MinSize));