1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
36 #define DEBUG_TYPE "arm-subtarget"
38 #define GET_SUBTARGETINFO_TARGET_DESC
39 #define GET_SUBTARGETINFO_CTOR
40 #include "ARMGenSubtargetInfo.inc"
43 UseFusedMulOps("arm-use-mulops",
44 cl::init(true), cl::Hidden);
52 static cl::opt<ITMode>
53 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
55 cl::values(clEnumValN(DefaultIT, "arm-default-it",
56 "Generate IT block based on arch"),
57 clEnumValN(RestrictedIT, "arm-restrict-it",
58 "Disallow deprecated IT based on ARMv8"),
59 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
60 "Allow IT blocks based on ARMv7"),
63 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
64 /// so that we can use initializer lists for subtarget initialization.
65 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
67 initializeEnvironment();
68 initSubtargetFeatures(CPU, FS);
72 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
74 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
75 if (STI.isThumb1Only())
76 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
78 return new ARMFrameLowering(STI);
81 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
82 const std::string &FS,
83 const ARMBaseTargetMachine &TM, bool IsLittle)
84 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
85 ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
86 TargetTriple(TT), Options(TM.Options), TM(TM),
87 FrameLowering(initializeFrameLowering(CPU, FS)),
88 // At this point initializeSubtargetDependencies has been called so
89 // we can query directly.
90 InstrInfo(isThumb1Only()
91 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
93 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
94 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
97 void ARMSubtarget::initializeEnvironment() {
113 UseNEONForSinglePrecisionFP = false;
114 UseMulOps = UseFusedMulOps;
116 HasVMLxForwarding = false;
119 UseSoftFloat = false;
124 SupportsTailCall = false;
127 HasHardwareDivide = false;
128 HasHardwareDivideInARM = false;
129 HasT2ExtractPack = false;
130 HasDataBarrier = false;
131 Pref32BitThumb = false;
132 AvoidCPSRPartialUpdate = false;
133 AvoidMOVsShifterOperand = false;
135 HasMPExtension = false;
136 HasVirtualization = false;
139 HasTrustZone = false;
142 HasZeroCycleZeroing = false;
146 GenLongCalls = false;
147 UnsafeFPMath = false;
150 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
151 if (CPUString.empty()) {
152 if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s"))
153 // Default to the Swift CPU when targeting armv7s/thumbv7s.
156 CPUString = "generic";
159 // Insert the architecture feature derived from the target triple into the
160 // feature string. This is important for setting features that are implied
161 // based on the architecture version.
162 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
165 ArchFS = (Twine(ArchFS) + "," + FS).str();
169 ParseSubtargetFeatures(CPUString, ArchFS);
171 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
172 // Assert this for now to make the change obvious.
173 assert(hasV6T2Ops() || !hasThumb2());
175 // Keep a pointer to static instruction cost data for the specified CPU.
176 SchedModel = getSchedModelForCPU(CPUString);
178 // Initialize scheduling itinerary for the specified CPU.
179 InstrItins = getInstrItineraryForCPU(CPUString);
181 // FIXME: this is invalid for WindowsCE
182 if (isTargetWindows())
191 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
193 SupportsTailCall = !isThumb1Only();
197 RestrictIT = hasV8Ops();
207 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
208 const FeatureBitset &Bits = getFeatureBits();
209 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
210 (Options.UnsafeFPMath || isTargetDarwin()))
211 UseNEONForSinglePrecisionFP = true;
214 bool ARMSubtarget::isAPCS_ABI() const {
215 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
216 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
218 bool ARMSubtarget::isAAPCS_ABI() const {
219 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
220 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS;
223 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
225 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
226 Reloc::Model RelocM) const {
227 if (RelocM == Reloc::Static)
230 bool isDef = GV->isStrongDefinitionForLinker();
232 if (!isTargetMachO()) {
233 // Extra load is needed for all externally visible.
234 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
238 // If this is a strong reference to a definition, it is definitely not
243 // Unless we have a symbol with hidden visibility, we have to go through a
244 // normal $non_lazy_ptr stub because this symbol might be resolved late.
245 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
248 if (RelocM == Reloc::PIC_) {
249 // If symbol visibility is hidden, we have a stub for common symbol
250 // references and external declarations.
251 if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
252 // Hidden $non_lazy_ptr reference.
260 unsigned ARMSubtarget::getMispredictionPenalty() const {
261 return SchedModel.MispredictPenalty;
264 bool ARMSubtarget::hasSinCos() const {
265 return getTargetTriple().isiOS() && !getTargetTriple().isOSVersionLT(7, 0);
268 bool ARMSubtarget::enableMachineScheduler() const {
269 // Enable the MachineScheduler before register allocation for out-of-order
270 // architectures where we do not use the PostRA scheduler anymore (for now
271 // restricted to swift).
272 return getSchedModel().isOutOfOrder() && isSwift();
275 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
276 bool ARMSubtarget::enablePostRAScheduler() const {
277 // No need for PostRA scheduling on out of order CPUs (for now restricted to
279 if (getSchedModel().isOutOfOrder() && isSwift())
281 return (!isThumb() || hasThumb2());
284 bool ARMSubtarget::enableAtomicExpand() const {
285 return hasAnyDataBarrier() && !isThumb1Only();
288 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
289 return isSwift() && !MF.getFunction()->optForMinSize();
292 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
293 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
294 // immediates as it is inherently position independent, and may be out of
296 return !NoMovt && hasV6T2Ops() &&
297 (isTargetWindows() || !MF.getFunction()->optForMinSize());
300 bool ARMSubtarget::useFastISel() const {
301 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
302 return TM.Options.EnableFastISel &&
303 ((isTargetMachO() && !isThumb1Only()) ||
304 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));