1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetOptions.h"
24 #define GET_SUBTARGETINFO_TARGET_DESC
25 #define GET_SUBTARGETINFO_CTOR
26 #include "ARMGenSubtargetInfo.inc"
31 ReserveR9("arm-reserve-r9", cl::Hidden,
32 cl::desc("Reserve R9, making it unavailable as GPR"));
35 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
38 UseFusedMulOps("arm-use-mulops",
39 cl::init(true), cl::Hidden);
42 StrictAlign("arm-strict-align", cl::Hidden,
43 cl::desc("Disallow all unaligned memory accesses"));
45 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
46 const std::string &FS, const TargetOptions &Options)
47 : ARMGenSubtargetInfo(TT, CPU, FS)
48 , ARMProcFamily(Others)
53 , TargetABI(ARM_ABI_APCS) {
54 initializeEnvironment();
55 resetSubtargetFeatures(CPU, FS);
58 void ARMSubtarget::initializeEnvironment() {
69 UseNEONForSinglePrecisionFP = false;
70 UseMulOps = UseFusedMulOps;
72 HasVMLxForwarding = false;
78 PostRAScheduler = false;
79 IsR9Reserved = ReserveR9;
81 SupportsTailCall = false;
84 HasHardwareDivide = false;
85 HasHardwareDivideInARM = false;
86 HasT2ExtractPack = false;
87 HasDataBarrier = false;
88 Pref32BitThumb = false;
89 AvoidCPSRPartialUpdate = false;
90 AvoidMOVsShifterOperand = false;
92 HasMPExtension = false;
94 AllowsUnalignedMem = false;
100 void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
101 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
102 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
104 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
107 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
109 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
111 initializeEnvironment();
112 resetSubtargetFeatures(CPU, FS);
116 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
117 if (CPUString.empty())
118 CPUString = "generic";
120 // Insert the architecture feature derived from the target triple into the
121 // feature string. This is important for setting features that are implied
122 // based on the architecture version.
123 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
127 ArchFS = ArchFS + "," + FS.str();
131 ParseSubtargetFeatures(CPUString, ArchFS);
133 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
134 // ARM version or CPU and then remove this.
135 if (!HasV6T2Ops && hasThumb2())
136 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
138 // Keep a pointer to static instruction cost data for the specified CPU.
139 SchedModel = getSchedModelForCPU(CPUString);
141 // Initialize scheduling itinerary for the specified CPU.
142 InstrItins = getInstrItineraryForCPU(CPUString);
144 if ((TargetTriple.getTriple().find("eabi") != std::string::npos) ||
145 (isTargetIOS() && isMClass()))
146 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
147 // Darwin-EABI conforms to AACPS but not the rest of EABI.
148 TargetABI = ARM_ABI_AAPCS;
154 UseMovt = hasV6T2Ops();
156 IsR9Reserved = ReserveR9 | !HasV6Ops;
157 UseMovt = DarwinUseMOVT && hasV6T2Ops();
158 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
161 if (!isThumb() || hasThumb2())
162 PostRAScheduler = true;
164 // v6+ may or may not support unaligned mem access depending on the system
166 if (!StrictAlign && hasV6Ops() && isTargetDarwin())
167 AllowsUnalignedMem = true;
169 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
170 uint64_t Bits = getFeatureBits();
171 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
172 (Options.UnsafeFPMath || isTargetDarwin()))
173 UseNEONForSinglePrecisionFP = true;
176 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
178 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
179 Reloc::Model RelocM) const {
180 if (RelocM == Reloc::Static)
183 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
185 bool isDecl = GV->hasAvailableExternallyLinkage();
186 if (GV->isDeclaration() && !GV->isMaterializable())
189 if (!isTargetDarwin()) {
190 // Extra load is needed for all externally visible.
191 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
195 if (RelocM == Reloc::PIC_) {
196 // If this is a strong reference to a definition, it is definitely not
198 if (!isDecl && !GV->isWeakForLinker())
201 // Unless we have a symbol with hidden visibility, we have to go through a
202 // normal $non_lazy_ptr stub because this symbol might be resolved late.
203 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
206 // If symbol visibility is hidden, we have a stub for common symbol
207 // references and external declarations.
208 if (isDecl || GV->hasCommonLinkage())
209 // Hidden $non_lazy_ptr reference.
214 // If this is a strong reference to a definition, it is definitely not
216 if (!isDecl && !GV->isWeakForLinker())
219 // Unless we have a symbol with hidden visibility, we have to go through a
220 // normal $non_lazy_ptr stub because this symbol might be resolved late.
221 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
229 unsigned ARMSubtarget::getMispredictionPenalty() const {
230 return SchedModel->MispredictPenalty;
233 bool ARMSubtarget::enablePostRAScheduler(
234 CodeGenOpt::Level OptLevel,
235 TargetSubtargetInfo::AntiDepBreakMode& Mode,
236 RegClassVector& CriticalPathRCs) const {
237 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
238 CriticalPathRCs.clear();
239 CriticalPathRCs.push_back(&ARM::GPRRegClass);
240 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;