1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "llvm/GlobalValue.h"
17 #include "llvm/Target/TargetSubtargetInfo.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/ADT/SmallVector.h"
21 #define GET_SUBTARGETINFO_TARGET_DESC
22 #define GET_SUBTARGETINFO_CTOR
23 #include "ARMGenSubtargetInfo.inc"
28 ReserveR9("arm-reserve-r9", cl::Hidden,
29 cl::desc("Reserve R9, making it unavailable as GPR"));
32 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
35 StrictAlign("arm-strict-align", cl::Hidden,
36 cl::desc("Disallow all unaligned memory accesses"));
38 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
39 const std::string &FS)
40 : ARMGenSubtargetInfo(TT, CPU, FS)
41 , ARMProcFamily(Others)
53 , UseNEONForSinglePrecisionFP(false)
55 , HasVMLxForwarding(false)
61 , PostRAScheduler(false)
62 , IsR9Reserved(ReserveR9)
64 , SupportsTailCall(false)
67 , HasHardwareDivide(false)
68 , HasT2ExtractPack(false)
69 , HasDataBarrier(false)
70 , Pref32BitThumb(false)
71 , AvoidCPSRPartialUpdate(false)
72 , HasMPExtension(false)
74 , AllowsUnalignedMem(false)
79 , TargetABI(ARM_ABI_APCS) {
80 // Determine default and user specified characteristics
81 if (CPUString.empty())
82 CPUString = "generic";
84 // Insert the architecture feature derived from the target triple into the
85 // feature string. This is important for setting features that are implied
86 // based on the architecture version.
87 std::string ArchFS = ARM_MC::ParseARMTriple(TT);
90 ArchFS = ArchFS + "," + FS;
94 ParseSubtargetFeatures(CPUString, ArchFS);
96 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
97 // ARM version or CPU and then remove this.
98 if (!HasV6T2Ops && hasThumb2())
99 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
101 // Initialize scheduling itinerary for the specified CPU.
102 InstrItins = getInstrItineraryForCPU(CPUString);
104 // After parsing Itineraries, set ItinData.IssueWidth.
107 if (TT.find("eabi") != std::string::npos)
108 TargetABI = ARM_ABI_AAPCS;
114 UseMovt = hasV6T2Ops();
116 IsR9Reserved = ReserveR9 | !HasV6Ops;
117 UseMovt = DarwinUseMOVT && hasV6T2Ops();
118 const Triple &T = getTargetTriple();
119 SupportsTailCall = !T.isOSVersionLT(5, 0);
122 if (!isThumb() || hasThumb2())
123 PostRAScheduler = true;
125 // v6+ may or may not support unaligned mem access depending on the system
127 if (!StrictAlign && hasV6Ops() && isTargetDarwin())
128 AllowsUnalignedMem = true;
131 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
133 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
134 Reloc::Model RelocM) const {
135 if (RelocM == Reloc::Static)
138 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
140 bool isDecl = GV->hasAvailableExternallyLinkage();
141 if (GV->isDeclaration() && !GV->isMaterializable())
144 if (!isTargetDarwin()) {
145 // Extra load is needed for all externally visible.
146 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
150 if (RelocM == Reloc::PIC_) {
151 // If this is a strong reference to a definition, it is definitely not
153 if (!isDecl && !GV->isWeakForLinker())
156 // Unless we have a symbol with hidden visibility, we have to go through a
157 // normal $non_lazy_ptr stub because this symbol might be resolved late.
158 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
161 // If symbol visibility is hidden, we have a stub for common symbol
162 // references and external declarations.
163 if (isDecl || GV->hasCommonLinkage())
164 // Hidden $non_lazy_ptr reference.
169 // If this is a strong reference to a definition, it is definitely not
171 if (!isDecl && !GV->isWeakForLinker())
174 // Unless we have a symbol with hidden visibility, we have to go through a
175 // normal $non_lazy_ptr stub because this symbol might be resolved late.
176 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
184 unsigned ARMSubtarget::getMispredictionPenalty() const {
185 // If we have a reasonable estimate of the pipeline depth, then we can
186 // estimate the penalty of a misprediction based on that.
189 else if (isCortexA9())
192 // Otherwise, just return a sensible default.
196 void ARMSubtarget::computeIssueWidth() {
197 unsigned allStage1Units = 0;
198 for (const InstrItinerary *itin = InstrItins.Itineraries;
199 itin->FirstStage != ~0U; ++itin) {
200 const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
201 allStage1Units |= IS->getUnits();
203 InstrItins.IssueWidth = 0;
204 while (allStage1Units) {
205 ++InstrItins.IssueWidth;
206 // clear the lowest bit
207 allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
209 assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
212 bool ARMSubtarget::enablePostRAScheduler(
213 CodeGenOpt::Level OptLevel,
214 TargetSubtargetInfo::AntiDepBreakMode& Mode,
215 RegClassVector& CriticalPathRCs) const {
216 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
217 CriticalPathRCs.clear();
218 CriticalPathRCs.push_back(&ARM::GPRRegClass);
219 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;