1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
23 #define GET_SUBTARGETINFO_TARGET_DESC
24 #define GET_SUBTARGETINFO_CTOR
25 #include "ARMGenSubtargetInfo.inc"
30 ReserveR9("arm-reserve-r9", cl::Hidden,
31 cl::desc("Reserve R9, making it unavailable as GPR"));
34 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
37 UseFusedMulOps("arm-use-mulops",
38 cl::init(true), cl::Hidden);
41 StrictAlign("arm-strict-align", cl::Hidden,
42 cl::desc("Disallow all unaligned memory accesses"));
44 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
45 const std::string &FS)
46 : ARMGenSubtargetInfo(TT, CPU, FS)
47 , ARMProcFamily(Others)
58 , UseNEONForSinglePrecisionFP(false)
59 , UseMulOps(UseFusedMulOps)
61 , HasVMLxForwarding(false)
67 , PostRAScheduler(false)
68 , IsR9Reserved(ReserveR9)
70 , SupportsTailCall(false)
73 , HasHardwareDivide(false)
74 , HasHardwareDivideInARM(false)
75 , HasT2ExtractPack(false)
76 , HasDataBarrier(false)
77 , Pref32BitThumb(false)
78 , AvoidCPSRPartialUpdate(false)
79 , AvoidMOVsShifterOperand(false)
81 , HasMPExtension(false)
83 , AllowsUnalignedMem(false)
89 , TargetABI(ARM_ABI_APCS) {
90 resetSubtargetFeatures(CPU, FS);
93 void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
94 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
95 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
97 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
100 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
102 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
104 resetSubtargetFeatures(CPU, FS);
107 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
108 if (CPUString.empty())
109 CPUString = "generic";
111 // Insert the architecture feature derived from the target triple into the
112 // feature string. This is important for setting features that are implied
113 // based on the architecture version.
114 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
118 ArchFS = ArchFS + "," + FS.str();
122 ParseSubtargetFeatures(CPUString, ArchFS);
124 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
125 // ARM version or CPU and then remove this.
126 if (!HasV6T2Ops && hasThumb2())
127 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
129 // Keep a pointer to static instruction cost data for the specified CPU.
130 SchedModel = getSchedModelForCPU(CPUString);
132 // Initialize scheduling itinerary for the specified CPU.
133 InstrItins = getInstrItineraryForCPU(CPUString);
135 if ((TargetTriple.getTriple().find("eabi") != std::string::npos) ||
136 (isTargetIOS() && isMClass()))
137 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
138 // Darwin-EABI conforms to AACPS but not the rest of EABI.
139 TargetABI = ARM_ABI_AAPCS;
145 UseMovt = hasV6T2Ops();
147 IsR9Reserved = ReserveR9 | !HasV6Ops;
148 UseMovt = DarwinUseMOVT && hasV6T2Ops();
149 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
152 if (!isThumb() || hasThumb2())
153 PostRAScheduler = true;
155 // v6+ may or may not support unaligned mem access depending on the system
157 if (!StrictAlign && hasV6Ops() && isTargetDarwin())
158 AllowsUnalignedMem = true;
161 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
163 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
164 Reloc::Model RelocM) const {
165 if (RelocM == Reloc::Static)
168 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
170 bool isDecl = GV->hasAvailableExternallyLinkage();
171 if (GV->isDeclaration() && !GV->isMaterializable())
174 if (!isTargetDarwin()) {
175 // Extra load is needed for all externally visible.
176 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
180 if (RelocM == Reloc::PIC_) {
181 // If this is a strong reference to a definition, it is definitely not
183 if (!isDecl && !GV->isWeakForLinker())
186 // Unless we have a symbol with hidden visibility, we have to go through a
187 // normal $non_lazy_ptr stub because this symbol might be resolved late.
188 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
191 // If symbol visibility is hidden, we have a stub for common symbol
192 // references and external declarations.
193 if (isDecl || GV->hasCommonLinkage())
194 // Hidden $non_lazy_ptr reference.
199 // If this is a strong reference to a definition, it is definitely not
201 if (!isDecl && !GV->isWeakForLinker())
204 // Unless we have a symbol with hidden visibility, we have to go through a
205 // normal $non_lazy_ptr stub because this symbol might be resolved late.
206 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
214 unsigned ARMSubtarget::getMispredictionPenalty() const {
215 return SchedModel->MispredictPenalty;
218 bool ARMSubtarget::enablePostRAScheduler(
219 CodeGenOpt::Level OptLevel,
220 TargetSubtargetInfo::AntiDepBreakMode& Mode,
221 RegClassVector& CriticalPathRCs) const {
222 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
223 CriticalPathRCs.clear();
224 CriticalPathRCs.push_back(&ARM::GPRRegClass);
225 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;