1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetOptions.h"
24 #define GET_SUBTARGETINFO_TARGET_DESC
25 #define GET_SUBTARGETINFO_CTOR
26 #include "ARMGenSubtargetInfo.inc"
31 ReserveR9("arm-reserve-r9", cl::Hidden,
32 cl::desc("Reserve R9, making it unavailable as GPR"));
35 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
38 UseFusedMulOps("arm-use-mulops",
39 cl::init(true), cl::Hidden);
47 static cl::opt<AlignMode>
48 Align(cl::desc("Load/store alignment support"),
49 cl::Hidden, cl::init(DefaultAlign),
51 clEnumValN(DefaultAlign, "arm-default-align",
52 "Generate unaligned accesses only on hardware/OS "
53 "combinations that are known to support them"),
54 clEnumValN(StrictAlign, "arm-strict-align",
55 "Disallow all unaligned memory accesses"),
56 clEnumValN(NoStrictAlign, "arm-no-strict-align",
57 "Allow unaligned memory accesses"),
60 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
61 const std::string &FS, const TargetOptions &Options)
62 : ARMGenSubtargetInfo(TT, CPU, FS)
63 , ARMProcFamily(Others)
68 , TargetABI(ARM_ABI_APCS) {
69 initializeEnvironment();
70 resetSubtargetFeatures(CPU, FS);
73 void ARMSubtarget::initializeEnvironment() {
86 UseNEONForSinglePrecisionFP = false;
87 UseMulOps = UseFusedMulOps;
89 HasVMLxForwarding = false;
95 PostRAScheduler = false;
96 IsR9Reserved = ReserveR9;
98 SupportsTailCall = false;
101 HasHardwareDivide = false;
102 HasHardwareDivideInARM = false;
103 HasT2ExtractPack = false;
104 HasDataBarrier = false;
105 Pref32BitThumb = false;
106 AvoidCPSRPartialUpdate = false;
107 AvoidMOVsShifterOperand = false;
109 HasMPExtension = false;
112 HasTrustZone = false;
113 AllowsUnalignedMem = false;
116 UnsafeFPMath = false;
119 void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
120 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
121 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
123 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
126 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
128 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
130 initializeEnvironment();
131 resetSubtargetFeatures(CPU, FS);
135 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
136 if (CPUString.empty()) {
137 if (isTargetIOS() && TargetTriple.getArchName().endswith("v7s"))
138 // Default to the Swift CPU when targeting armv7s/thumbv7s.
141 CPUString = "generic";
144 // Insert the architecture feature derived from the target triple into the
145 // feature string. This is important for setting features that are implied
146 // based on the architecture version.
147 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
151 ArchFS = ArchFS + "," + FS.str();
155 ParseSubtargetFeatures(CPUString, ArchFS);
157 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
158 // ARM version or CPU and then remove this.
159 if (!HasV6T2Ops && hasThumb2())
160 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
162 // Keep a pointer to static instruction cost data for the specified CPU.
163 SchedModel = getSchedModelForCPU(CPUString);
165 // Initialize scheduling itinerary for the specified CPU.
166 InstrItins = getInstrItineraryForCPU(CPUString);
168 if ((TargetTriple.getTriple().find("eabi") != std::string::npos) ||
169 (isTargetIOS() && isMClass()))
170 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
171 // Darwin-EABI conforms to AACPS but not the rest of EABI.
172 TargetABI = ARM_ABI_AAPCS;
177 UseMovt = hasV6T2Ops() && ArmUseMOVT;
179 if (!isTargetIOS()) {
180 IsR9Reserved = ReserveR9;
182 IsR9Reserved = ReserveR9 | !HasV6Ops;
183 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
186 if (!isThumb() || hasThumb2())
187 PostRAScheduler = true;
191 // Assume pre-ARMv6 doesn't support unaligned accesses.
193 // ARMv6 may or may not support unaligned accesses depending on the
194 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
195 // Darwin targets support unaligned accesses, and others don't.
197 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
198 // which raises an alignment fault on unaligned accesses. Linux
199 // defaults this bit to 0 and handles it as a system-wide (not
200 // per-process) setting. It is therefore safe to assume that ARMv7+
201 // Linux targets support unaligned accesses. The same goes for NaCl.
203 // The above behavior is consistent with GCC.
204 AllowsUnalignedMem = (
205 (hasV7Ops() && (isTargetLinux() || isTargetNaCl())) ||
206 (hasV6Ops() && isTargetDarwin()));
209 AllowsUnalignedMem = false;
212 AllowsUnalignedMem = true;
216 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
217 uint64_t Bits = getFeatureBits();
218 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
219 (Options.UnsafeFPMath || isTargetDarwin()))
220 UseNEONForSinglePrecisionFP = true;
223 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
225 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
226 Reloc::Model RelocM) const {
227 if (RelocM == Reloc::Static)
230 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
232 bool isDecl = GV->hasAvailableExternallyLinkage();
233 if (GV->isDeclaration() && !GV->isMaterializable())
236 if (!isTargetDarwin()) {
237 // Extra load is needed for all externally visible.
238 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
242 if (RelocM == Reloc::PIC_) {
243 // If this is a strong reference to a definition, it is definitely not
245 if (!isDecl && !GV->isWeakForLinker())
248 // Unless we have a symbol with hidden visibility, we have to go through a
249 // normal $non_lazy_ptr stub because this symbol might be resolved late.
250 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
253 // If symbol visibility is hidden, we have a stub for common symbol
254 // references and external declarations.
255 if (isDecl || GV->hasCommonLinkage())
256 // Hidden $non_lazy_ptr reference.
261 // If this is a strong reference to a definition, it is definitely not
263 if (!isDecl && !GV->isWeakForLinker())
266 // Unless we have a symbol with hidden visibility, we have to go through a
267 // normal $non_lazy_ptr stub because this symbol might be resolved late.
268 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
276 unsigned ARMSubtarget::getMispredictionPenalty() const {
277 return SchedModel->MispredictPenalty;
280 bool ARMSubtarget::enablePostRAScheduler(
281 CodeGenOpt::Level OptLevel,
282 TargetSubtargetInfo::AntiDepBreakMode& Mode,
283 RegClassVector& CriticalPathRCs) const {
284 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
285 CriticalPathRCs.clear();
286 CriticalPathRCs.push_back(&ARM::GPRRegClass);
287 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;