1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
36 #define DEBUG_TYPE "arm-subtarget"
38 #define GET_SUBTARGETINFO_TARGET_DESC
39 #define GET_SUBTARGETINFO_CTOR
40 #include "ARMGenSubtargetInfo.inc"
43 ReserveR9("arm-reserve-r9", cl::Hidden,
44 cl::desc("Reserve R9, making it unavailable as GPR"));
47 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
50 UseFusedMulOps("arm-use-mulops",
51 cl::init(true), cl::Hidden);
61 static cl::opt<AlignMode>
62 Align(cl::desc("Load/store alignment support"),
63 cl::Hidden, cl::init(DefaultAlign),
65 clEnumValN(DefaultAlign, "arm-default-align",
66 "Generate unaligned accesses only on hardware/OS "
67 "combinations that are known to support them"),
68 clEnumValN(StrictAlign, "arm-strict-align",
69 "Disallow all unaligned memory accesses"),
70 clEnumValN(NoStrictAlign, "arm-no-strict-align",
71 "Allow unaligned memory accesses"),
80 static cl::opt<ITMode>
81 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
83 cl::values(clEnumValN(DefaultIT, "arm-default-it",
84 "Generate IT block based on arch"),
85 clEnumValN(RestrictedIT, "arm-restrict-it",
86 "Disallow deprecated IT based on ARMv8"),
87 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
88 "Allow IT blocks based on ARMv7"),
91 static std::string computeDataLayout(ARMSubtarget &ST) {
101 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
103 // Pointers are 32 bits and aligned to 32 bits.
106 // ABIs other than APCS have 64 bit integers with natural alignment.
107 if (!ST.isAPCS_ABI())
110 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
111 // bits, others to 64 bits. We always try to align to 64 bits.
115 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
116 // to 64. We always ty to give them natural alignment.
118 Ret += "-v64:32:64-v128:32:128";
120 Ret += "-v128:64:128";
122 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
123 // particular hardware support on 32-bit ARM).
126 // Integer registers are 32 bits.
129 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
130 // aligned everywhere else.
131 if (ST.isTargetNaCl())
133 else if (ST.isAAPCS_ABI())
141 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
142 /// so that we can use initializer lists for subtarget initialization.
143 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
145 initializeEnvironment();
146 initSubtargetFeatures(CPU, FS);
150 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
151 const std::string &FS, const ARMBaseTargetMachine &TM,
153 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
154 ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
155 TargetTriple(TT), Options(TM.Options), TM(TM),
156 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
158 InstrInfo(isThumb1Only()
159 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
161 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
162 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
164 FrameLowering(!isThumb1Only()
165 ? new ARMFrameLowering(*this)
166 : (ARMFrameLowering *)new Thumb1FrameLowering(*this)) {}
168 void ARMSubtarget::initializeEnvironment() {
182 UseNEONForSinglePrecisionFP = false;
183 UseMulOps = UseFusedMulOps;
185 HasVMLxForwarding = false;
190 IsR9Reserved = ReserveR9;
192 SupportsTailCall = false;
195 HasHardwareDivide = false;
196 HasHardwareDivideInARM = false;
197 HasT2ExtractPack = false;
198 HasDataBarrier = false;
199 Pref32BitThumb = false;
200 AvoidCPSRPartialUpdate = false;
201 AvoidMOVsShifterOperand = false;
203 HasMPExtension = false;
204 HasVirtualization = false;
207 HasTrustZone = false;
210 HasZeroCycleZeroing = false;
211 AllowsUnalignedMem = false;
214 UnsafeFPMath = false;
217 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
218 if (CPUString.empty()) {
219 if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s"))
220 // Default to the Swift CPU when targeting armv7s/thumbv7s.
223 CPUString = "generic";
226 // Insert the architecture feature derived from the target triple into the
227 // feature string. This is important for setting features that are implied
228 // based on the architecture version.
230 ARM_MC::ParseARMTriple(TargetTriple.getTriple(), CPUString);
233 ArchFS = ArchFS + "," + FS.str();
237 ParseSubtargetFeatures(CPUString, ArchFS);
239 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
240 // Assert this for now to make the change obvious.
241 assert(hasV6T2Ops() || !hasThumb2());
243 // Keep a pointer to static instruction cost data for the specified CPU.
244 SchedModel = getSchedModelForCPU(CPUString);
246 // Initialize scheduling itinerary for the specified CPU.
247 InstrItins = getInstrItineraryForCPU(CPUString);
249 // FIXME: this is invalid for WindowsCE
250 if (isTargetWindows())
258 UseMovt = hasV6T2Ops() && ArmUseMOVT;
260 if (isTargetMachO()) {
261 IsR9Reserved = ReserveR9 || !HasV6Ops;
262 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
264 IsR9Reserved = ReserveR9;
265 SupportsTailCall = !isThumb1Only();
268 if (Align == DefaultAlign) {
269 // Assume pre-ARMv6 doesn't support unaligned accesses.
271 // ARMv6 may or may not support unaligned accesses depending on the
272 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
273 // Darwin and NetBSD targets support unaligned accesses, and others don't.
275 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
276 // which raises an alignment fault on unaligned accesses. Linux
277 // defaults this bit to 0 and handles it as a system-wide (not
278 // per-process) setting. It is therefore safe to assume that ARMv7+
279 // Linux targets support unaligned accesses. The same goes for NaCl.
281 // The above behavior is consistent with GCC.
283 (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
284 isTargetNetBSD())) ||
285 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
287 AllowsUnalignedMem = !(Align == StrictAlign);
290 // No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
292 AllowsUnalignedMem = false;
296 RestrictIT = hasV8Ops() ? true : false;
306 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
307 uint64_t Bits = getFeatureBits();
308 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
309 (Options.UnsafeFPMath || isTargetDarwin()))
310 UseNEONForSinglePrecisionFP = true;
313 bool ARMSubtarget::isAPCS_ABI() const {
314 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
315 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
317 bool ARMSubtarget::isAAPCS_ABI() const {
318 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
319 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS;
322 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
324 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
325 Reloc::Model RelocM) const {
326 if (RelocM == Reloc::Static)
329 bool isDecl = GV->isDeclarationForLinker();
331 if (!isTargetMachO()) {
332 // Extra load is needed for all externally visible.
333 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
337 if (RelocM == Reloc::PIC_) {
338 // If this is a strong reference to a definition, it is definitely not
340 if (!isDecl && !GV->isWeakForLinker())
343 // Unless we have a symbol with hidden visibility, we have to go through a
344 // normal $non_lazy_ptr stub because this symbol might be resolved late.
345 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
348 // If symbol visibility is hidden, we have a stub for common symbol
349 // references and external declarations.
350 if (isDecl || GV->hasCommonLinkage())
351 // Hidden $non_lazy_ptr reference.
356 // If this is a strong reference to a definition, it is definitely not
358 if (!isDecl && !GV->isWeakForLinker())
361 // Unless we have a symbol with hidden visibility, we have to go through a
362 // normal $non_lazy_ptr stub because this symbol might be resolved late.
363 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
371 unsigned ARMSubtarget::getMispredictionPenalty() const {
372 return SchedModel.MispredictPenalty;
375 bool ARMSubtarget::hasSinCos() const {
376 return getTargetTriple().isiOS() && !getTargetTriple().isOSVersionLT(7, 0);
379 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
380 bool ARMSubtarget::enablePostMachineScheduler() const {
381 return (!isThumb() || hasThumb2());
384 bool ARMSubtarget::enableAtomicExpand() const {
385 return hasAnyDataBarrier() && !isThumb1Only();
388 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
389 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
390 // immediates as it is inherently position independent, and may be out of
392 return UseMovt && (isTargetWindows() ||
393 !MF.getFunction()->getAttributes().hasAttribute(
394 AttributeSet::FunctionIndex, Attribute::MinSize));