1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetOptions.h"
24 #define GET_SUBTARGETINFO_TARGET_DESC
25 #define GET_SUBTARGETINFO_CTOR
26 #include "ARMGenSubtargetInfo.inc"
31 ReserveR9("arm-reserve-r9", cl::Hidden,
32 cl::desc("Reserve R9, making it unavailable as GPR"));
35 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
38 UseFusedMulOps("arm-use-mulops",
39 cl::init(true), cl::Hidden);
47 static cl::opt<AlignMode>
48 Align(cl::desc("Load/store alignment support"),
49 cl::Hidden, cl::init(DefaultAlign),
51 clEnumValN(DefaultAlign, "arm-default-align",
52 "Generate unaligned accesses only on hardware/OS "
53 "combinations that are known to support them"),
54 clEnumValN(StrictAlign, "arm-strict-align",
55 "Disallow all unaligned memory accesses"),
56 clEnumValN(NoStrictAlign, "arm-no-strict-align",
57 "Allow unaligned memory accesses"),
60 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
61 const std::string &FS, const TargetOptions &Options)
62 : ARMGenSubtargetInfo(TT, CPU, FS)
63 , ARMProcFamily(Others)
68 , TargetABI(ARM_ABI_APCS) {
69 initializeEnvironment();
70 resetSubtargetFeatures(CPU, FS);
73 void ARMSubtarget::initializeEnvironment() {
86 UseNEONForSinglePrecisionFP = false;
87 UseMulOps = UseFusedMulOps;
89 HasVMLxForwarding = false;
95 PostRAScheduler = false;
96 IsR9Reserved = ReserveR9;
98 SupportsTailCall = false;
101 HasHardwareDivide = false;
102 HasHardwareDivideInARM = false;
103 HasT2ExtractPack = false;
104 HasDataBarrier = false;
105 Pref32BitThumb = false;
106 AvoidCPSRPartialUpdate = false;
107 AvoidMOVsShifterOperand = false;
109 HasMPExtension = false;
112 HasTrustZone = false;
114 AllowsUnalignedMem = false;
117 UnsafeFPMath = false;
120 void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
121 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
122 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
124 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
127 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
129 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
131 initializeEnvironment();
132 resetSubtargetFeatures(CPU, FS);
136 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
137 if (CPUString.empty()) {
138 if (isTargetIOS() && TargetTriple.getArchName().endswith("v7s"))
139 // Default to the Swift CPU when targeting armv7s/thumbv7s.
142 CPUString = "generic";
145 // Insert the architecture feature derived from the target triple into the
146 // feature string. This is important for setting features that are implied
147 // based on the architecture version.
148 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
152 ArchFS = ArchFS + "," + FS.str();
156 ParseSubtargetFeatures(CPUString, ArchFS);
158 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
159 // ARM version or CPU and then remove this.
160 if (!HasV6T2Ops && hasThumb2())
161 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
163 // Keep a pointer to static instruction cost data for the specified CPU.
164 SchedModel = getSchedModelForCPU(CPUString);
166 // Initialize scheduling itinerary for the specified CPU.
167 InstrItins = getInstrItineraryForCPU(CPUString);
169 if ((TargetTriple.getTriple().find("eabi") != std::string::npos) ||
170 (isTargetIOS() && isMClass()))
171 // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
172 // Darwin-EABI conforms to AACPS but not the rest of EABI.
173 TargetABI = ARM_ABI_AAPCS;
178 UseMovt = hasV6T2Ops() && ArmUseMOVT;
180 if (!isTargetIOS()) {
181 IsR9Reserved = ReserveR9;
183 IsR9Reserved = ReserveR9 | !HasV6Ops;
184 SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
187 if (!isThumb() || hasThumb2())
188 PostRAScheduler = true;
192 // Assume pre-ARMv6 doesn't support unaligned accesses.
194 // ARMv6 may or may not support unaligned accesses depending on the
195 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
196 // Darwin targets support unaligned accesses, and others don't.
198 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
199 // which raises an alignment fault on unaligned accesses. Linux
200 // defaults this bit to 0 and handles it as a system-wide (not
201 // per-process) setting. It is therefore safe to assume that ARMv7+
202 // Linux targets support unaligned accesses. The same goes for NaCl.
204 // The above behavior is consistent with GCC.
205 AllowsUnalignedMem = (
206 (hasV7Ops() && (isTargetLinux() || isTargetNaCl())) ||
207 (hasV6Ops() && isTargetDarwin()));
210 AllowsUnalignedMem = false;
213 AllowsUnalignedMem = true;
217 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
218 uint64_t Bits = getFeatureBits();
219 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
220 (Options.UnsafeFPMath || isTargetDarwin()))
221 UseNEONForSinglePrecisionFP = true;
224 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
226 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
227 Reloc::Model RelocM) const {
228 if (RelocM == Reloc::Static)
231 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
233 bool isDecl = GV->hasAvailableExternallyLinkage();
234 if (GV->isDeclaration() && !GV->isMaterializable())
237 if (!isTargetDarwin()) {
238 // Extra load is needed for all externally visible.
239 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
243 if (RelocM == Reloc::PIC_) {
244 // If this is a strong reference to a definition, it is definitely not
246 if (!isDecl && !GV->isWeakForLinker())
249 // Unless we have a symbol with hidden visibility, we have to go through a
250 // normal $non_lazy_ptr stub because this symbol might be resolved late.
251 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
254 // If symbol visibility is hidden, we have a stub for common symbol
255 // references and external declarations.
256 if (isDecl || GV->hasCommonLinkage())
257 // Hidden $non_lazy_ptr reference.
262 // If this is a strong reference to a definition, it is definitely not
264 if (!isDecl && !GV->isWeakForLinker())
267 // Unless we have a symbol with hidden visibility, we have to go through a
268 // normal $non_lazy_ptr stub because this symbol might be resolved late.
269 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
277 unsigned ARMSubtarget::getMispredictionPenalty() const {
278 return SchedModel->MispredictPenalty;
281 bool ARMSubtarget::enablePostRAScheduler(
282 CodeGenOpt::Level OptLevel,
283 TargetSubtargetInfo::AntiDepBreakMode& Mode,
284 RegClassVector& CriticalPathRCs) const {
285 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
286 CriticalPathRCs.clear();
287 CriticalPathRCs.push_back(&ARM::GPRRegClass);
288 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;