1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMGenSubtarget.inc"
16 #include "llvm/GlobalValue.h"
17 #include "llvm/Target/TargetOptions.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/ADT/SmallVector.h"
23 ReserveR9("arm-reserve-r9", cl::Hidden,
24 cl::desc("Reserve R9, making it unavailable as GPR"));
27 UseMOVT("arm-use-movt",
28 cl::init(true), cl::Hidden);
31 StrictAlign("arm-strict-align", cl::Hidden,
32 cl::desc("Disallow all unaligned memory accesses"));
34 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
37 , ARMProcFamily(Others)
39 , UseNEONForSinglePrecisionFP(false)
45 , PostRAScheduler(false)
46 , IsR9Reserved(ReserveR9)
50 , HasHardwareDivide(false)
51 , HasT2ExtractPack(false)
52 , HasDataBarrier(false)
53 , Pref32BitThumb(false)
54 , HasMPExtension(false)
56 , AllowsUnalignedMem(false)
58 , CPUString("generic")
59 , TargetType(isELF) // Default to ELF unless otherwise specified.
60 , TargetABI(ARM_ABI_APCS) {
61 // Default to soft float ABI
62 if (FloatABIType == FloatABI::Default)
63 FloatABIType = FloatABI::Soft;
65 // Determine default and user specified characteristics
67 // When no arch is specified either by CPU or by attributes, make the default
69 const char *ARMArchFeature = "";
70 if (CPUString == "generic" && (FS.empty() || FS == "generic")) {
72 ARMArchFeature = ",+v4t";
75 // Set the boolean corresponding to the current target triple, or the default
76 // if one cannot be determined, to true.
77 unsigned Len = TT.length();
80 if (Len >= 5 && TT.substr(0, 4) == "armv")
82 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
84 if (Len >= 7 && TT[5] == 'v')
88 unsigned SubVer = TT[Idx];
89 if (SubVer >= '7' && SubVer <= '9') {
91 ARMArchFeature = ",+v7a";
92 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
94 ARMArchFeature = ",+v7m";
96 } else if (SubVer == '6') {
98 ARMArchFeature = ",+v6";
99 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
100 ARMArchVersion = V6T2;
101 ARMArchFeature = ",+v6t2";
103 } else if (SubVer == '5') {
104 ARMArchVersion = V5T;
105 ARMArchFeature = ",+v5t";
106 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
107 ARMArchVersion = V5TE;
108 ARMArchFeature = ",+v5te";
110 } else if (SubVer == '4') {
111 if (Len >= Idx+2 && TT[Idx+1] == 't') {
112 ARMArchVersion = V4T;
113 ARMArchFeature = ",+v4t";
122 if (TT.find("-darwin") != std::string::npos)
124 TargetType = isDarwin;
127 if (TT.find("eabi") != std::string::npos)
128 TargetABI = ARM_ABI_AAPCS;
130 // Parse features string. If the first entry in FS (the CPU) is missing,
131 // insert the architecture feature derived from the target triple. This is
132 // important for setting features that are implied based on the architecture
134 std::string FSWithArch;
136 FSWithArch = std::string(ARMArchFeature);
137 else if (FS.find(',') == 0)
138 FSWithArch = std::string(ARMArchFeature) + FS;
141 CPUString = ParseSubtargetFeatures(FSWithArch, CPUString);
143 // Thumb2 implies at least V6T2.
144 if (ARMArchVersion >= V6T2)
146 else if (ThumbMode >= Thumb2)
147 ARMArchVersion = V6T2;
152 if (isTargetDarwin())
153 IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
155 if (!isThumb() || hasThumb2())
156 PostRAScheduler = true;
158 // v6+ may or may not support unaligned mem access depending on the system
160 if (!StrictAlign && hasV6Ops() && isTargetDarwin())
161 AllowsUnalignedMem = true;
164 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
166 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
167 Reloc::Model RelocM) const {
168 if (RelocM == Reloc::Static)
171 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
173 bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
175 if (!isTargetDarwin()) {
176 // Extra load is needed for all externally visible.
177 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
181 if (RelocM == Reloc::PIC_) {
182 // If this is a strong reference to a definition, it is definitely not
184 if (!isDecl && !GV->isWeakForLinker())
187 // Unless we have a symbol with hidden visibility, we have to go through a
188 // normal $non_lazy_ptr stub because this symbol might be resolved late.
189 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
192 // If symbol visibility is hidden, we have a stub for common symbol
193 // references and external declarations.
194 if (isDecl || GV->hasCommonLinkage())
195 // Hidden $non_lazy_ptr reference.
200 // If this is a strong reference to a definition, it is definitely not
202 if (!isDecl && !GV->isWeakForLinker())
205 // Unless we have a symbol with hidden visibility, we have to go through a
206 // normal $non_lazy_ptr stub because this symbol might be resolved late.
207 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
215 unsigned ARMSubtarget::getMispredictionPenalty() const {
216 // If we have a reasonable estimate of the pipeline depth, then we can
217 // estimate the penalty of a misprediction based on that.
220 else if (isCortexA9())
223 // Otherwise, just return a sensible default.
227 bool ARMSubtarget::enablePostRAScheduler(
228 CodeGenOpt::Level OptLevel,
229 TargetSubtarget::AntiDepBreakMode& Mode,
230 RegClassVector& CriticalPathRCs) const {
231 Mode = TargetSubtarget::ANTIDEP_CRITICAL;
232 CriticalPathRCs.clear();
233 CriticalPathRCs.push_back(&ARM::GPRRegClass);
234 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;