1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMJITInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #define DEBUG_TYPE "arm-subtarget"
38 #define GET_SUBTARGETINFO_TARGET_DESC
39 #define GET_SUBTARGETINFO_CTOR
40 #include "ARMGenSubtargetInfo.inc"
43 ReserveR9("arm-reserve-r9", cl::Hidden,
44 cl::desc("Reserve R9, making it unavailable as GPR"));
47 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
50 UseFusedMulOps("arm-use-mulops",
51 cl::init(true), cl::Hidden);
61 static cl::opt<AlignMode>
62 Align(cl::desc("Load/store alignment support"),
63 cl::Hidden, cl::init(DefaultAlign),
65 clEnumValN(DefaultAlign, "arm-default-align",
66 "Generate unaligned accesses only on hardware/OS "
67 "combinations that are known to support them"),
68 clEnumValN(StrictAlign, "arm-strict-align",
69 "Disallow all unaligned memory accesses"),
70 clEnumValN(NoStrictAlign, "arm-no-strict-align",
71 "Allow unaligned memory accesses"),
80 static cl::opt<ITMode>
81 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
83 cl::values(clEnumValN(DefaultIT, "arm-default-it",
84 "Generate IT block based on arch"),
85 clEnumValN(RestrictedIT, "arm-restrict-it",
86 "Disallow deprecated IT based on ARMv8"),
87 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
88 "Allow IT blocks based on ARMv7"),
91 static std::string computeDataLayout(ARMSubtarget &ST) {
101 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
103 // Pointers are 32 bits and aligned to 32 bits.
106 // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
109 Ret += "-i1:8:32-i8:8:32-i16:16:32";
111 // ABIs other than APCS have 64 bit integers with natural alignment.
112 if (!ST.isAPCS_ABI())
115 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
116 // bits, others to 64 bits. We always try to align to 64 bits.
120 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
121 // to 64. We always ty to give them natural alignment.
123 Ret += "-v64:32:64-v128:32:128";
125 Ret += "-v128:64:128";
127 // On thumb and APCS, only try to align aggregates to 32 bits (the default is
129 if (ST.isThumb() || ST.isAPCS_ABI())
132 // Integer registers are 32 bits.
135 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
136 // aligned everywhere else.
137 if (ST.isTargetNaCl())
139 else if (ST.isAAPCS_ABI())
147 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
148 /// so that we can use initializer lists for subtarget initialization.
149 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
151 initializeEnvironment();
152 resetSubtargetFeatures(CPU, FS);
156 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
157 const std::string &FS, TargetMachine &TM,
158 bool IsLittle, const TargetOptions &Options)
159 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
160 ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
161 TargetTriple(TT), Options(Options), TargetABI(ARM_ABI_UNKNOWN),
162 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
163 TSInfo(DL), JITInfo(),
164 InstrInfo(isThumb1Only()
165 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
167 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
168 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
170 FrameLowering(!isThumb1Only()
171 ? new ARMFrameLowering(*this)
172 : (ARMFrameLowering *)new Thumb1FrameLowering(*this)) {}
174 void ARMSubtarget::initializeEnvironment() {
188 UseNEONForSinglePrecisionFP = false;
189 UseMulOps = UseFusedMulOps;
191 HasVMLxForwarding = false;
196 IsR9Reserved = ReserveR9;
198 SupportsTailCall = false;
201 HasHardwareDivide = false;
202 HasHardwareDivideInARM = false;
203 HasT2ExtractPack = false;
204 HasDataBarrier = false;
205 Pref32BitThumb = false;
206 AvoidCPSRPartialUpdate = false;
207 AvoidMOVsShifterOperand = false;
209 HasMPExtension = false;
210 HasVirtualization = false;
213 HasTrustZone = false;
216 HasZeroCycleZeroing = false;
217 AllowsUnalignedMem = false;
220 UnsafeFPMath = false;
223 void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
224 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
225 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
227 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
230 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
232 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
234 initializeEnvironment();
235 resetSubtargetFeatures(CPU, FS);
239 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
240 if (CPUString.empty()) {
241 if (isTargetIOS() && TargetTriple.getArchName().endswith("v7s"))
242 // Default to the Swift CPU when targeting armv7s/thumbv7s.
245 CPUString = "generic";
248 // Insert the architecture feature derived from the target triple into the
249 // feature string. This is important for setting features that are implied
250 // based on the architecture version.
251 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
255 ArchFS = ArchFS + "," + FS.str();
259 ParseSubtargetFeatures(CPUString, ArchFS);
261 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
262 // Assert this for now to make the change obvious.
263 assert(hasV6T2Ops() || !hasThumb2());
265 // Keep a pointer to static instruction cost data for the specified CPU.
266 SchedModel = getSchedModelForCPU(CPUString);
268 // Initialize scheduling itinerary for the specified CPU.
269 InstrItins = getInstrItineraryForCPU(CPUString);
271 if (TargetABI == ARM_ABI_UNKNOWN) {
272 switch (TargetTriple.getEnvironment()) {
273 case Triple::Android:
276 case Triple::GNUEABI:
277 case Triple::GNUEABIHF:
278 TargetABI = ARM_ABI_AAPCS;
281 if ((isTargetIOS() && isMClass()) ||
282 (TargetTriple.isOSBinFormatMachO() &&
283 TargetTriple.getOS() == Triple::UnknownOS))
284 TargetABI = ARM_ABI_AAPCS;
286 TargetABI = ARM_ABI_APCS;
291 // FIXME: this is invalid for WindowsCE
292 if (isTargetWindows()) {
293 TargetABI = ARM_ABI_AAPCS;
302 UseMovt = hasV6T2Ops() && ArmUseMOVT;
304 if (isTargetMachO()) {
305 IsR9Reserved = ReserveR9 | !HasV6Ops;
306 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
308 IsR9Reserved = ReserveR9;
309 SupportsTailCall = !isThumb1Only();
314 // Assume pre-ARMv6 doesn't support unaligned accesses.
316 // ARMv6 may or may not support unaligned accesses depending on the
317 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
318 // Darwin and NetBSD targets support unaligned accesses, and others don't.
320 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
321 // which raises an alignment fault on unaligned accesses. Linux
322 // defaults this bit to 0 and handles it as a system-wide (not
323 // per-process) setting. It is therefore safe to assume that ARMv7+
324 // Linux targets support unaligned accesses. The same goes for NaCl.
326 // The above behavior is consistent with GCC.
328 (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
329 isTargetNetBSD())) ||
330 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
331 // The one exception is cortex-m0, which despite being v6, does not
332 // support unaligned accesses. Rather than make the above boolean
333 // expression even more obtuse, just override the value here.
334 if (isThumb1Only() && isMClass())
335 AllowsUnalignedMem = false;
338 AllowsUnalignedMem = false;
341 AllowsUnalignedMem = true;
347 RestrictIT = hasV8Ops() ? true : false;
357 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
358 uint64_t Bits = getFeatureBits();
359 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
360 (Options.UnsafeFPMath || isTargetDarwin()))
361 UseNEONForSinglePrecisionFP = true;
364 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
366 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
367 Reloc::Model RelocM) const {
368 if (RelocM == Reloc::Static)
371 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
373 bool isDecl = GV->hasAvailableExternallyLinkage();
374 if (GV->isDeclaration() && !GV->isMaterializable())
377 if (!isTargetMachO()) {
378 // Extra load is needed for all externally visible.
379 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
383 if (RelocM == Reloc::PIC_) {
384 // If this is a strong reference to a definition, it is definitely not
386 if (!isDecl && !GV->isWeakForLinker())
389 // Unless we have a symbol with hidden visibility, we have to go through a
390 // normal $non_lazy_ptr stub because this symbol might be resolved late.
391 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
394 // If symbol visibility is hidden, we have a stub for common symbol
395 // references and external declarations.
396 if (isDecl || GV->hasCommonLinkage())
397 // Hidden $non_lazy_ptr reference.
402 // If this is a strong reference to a definition, it is definitely not
404 if (!isDecl && !GV->isWeakForLinker())
407 // Unless we have a symbol with hidden visibility, we have to go through a
408 // normal $non_lazy_ptr stub because this symbol might be resolved late.
409 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
417 unsigned ARMSubtarget::getMispredictionPenalty() const {
418 return SchedModel.MispredictPenalty;
421 bool ARMSubtarget::hasSinCos() const {
422 return getTargetTriple().getOS() == Triple::IOS &&
423 !getTargetTriple().isOSVersionLT(7, 0);
426 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
427 bool ARMSubtarget::enablePostMachineScheduler() const {
428 return (!isThumb() || hasThumb2());
431 bool ARMSubtarget::enableAtomicExpand() const {
432 return hasAnyDataBarrier() && !isThumb1Only();
435 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
436 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
437 // immediates as it is inherently position independent, and may be out of
439 return UseMovt && (isTargetWindows() ||
440 !MF.getFunction()->getAttributes().hasAttribute(
441 AttributeSet::FunctionIndex, Attribute::MinSize));