1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetOptions.h"
24 #define GET_SUBTARGETINFO_TARGET_DESC
25 #define GET_SUBTARGETINFO_CTOR
26 #include "ARMGenSubtargetInfo.inc"
31 ReserveR9("arm-reserve-r9", cl::Hidden,
32 cl::desc("Reserve R9, making it unavailable as GPR"));
35 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
38 UseFusedMulOps("arm-use-mulops",
39 cl::init(true), cl::Hidden);
47 static cl::opt<AlignMode>
48 Align(cl::desc("Load/store alignment support"),
49 cl::Hidden, cl::init(DefaultAlign),
51 clEnumValN(DefaultAlign, "arm-default-align",
52 "Generate unaligned accesses only on hardware/OS "
53 "combinations that are known to support them"),
54 clEnumValN(StrictAlign, "arm-strict-align",
55 "Disallow all unaligned memory accesses"),
56 clEnumValN(NoStrictAlign, "arm-no-strict-align",
57 "Allow unaligned memory accesses"),
66 static cl::opt<ITMode>
67 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
69 cl::values(clEnumValN(DefaultIT, "arm-default-it",
70 "Generate IT block based on arch"),
71 clEnumValN(RestrictedIT, "arm-restrict-it",
72 "Disallow deprecated IT based on ARMv8"),
73 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
74 "Allow IT blocks based on ARMv7"),
77 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
78 const std::string &FS, bool IsLittle,
79 const TargetOptions &Options)
80 : ARMGenSubtargetInfo(TT, CPU, FS)
81 , ARMProcFamily(Others)
88 , TargetABI(ARM_ABI_UNKNOWN) {
89 initializeEnvironment();
90 resetSubtargetFeatures(CPU, FS);
93 void ARMSubtarget::initializeEnvironment() {
108 UseNEONForSinglePrecisionFP = false;
109 UseMulOps = UseFusedMulOps;
111 HasVMLxForwarding = false;
116 PostRAScheduler = false;
117 IsR9Reserved = ReserveR9;
119 SupportsTailCall = false;
122 HasHardwareDivide = false;
123 HasHardwareDivideInARM = false;
124 HasT2ExtractPack = false;
125 HasDataBarrier = false;
126 Pref32BitThumb = false;
127 AvoidCPSRPartialUpdate = false;
128 AvoidMOVsShifterOperand = false;
130 HasMPExtension = false;
131 HasVirtualization = false;
134 HasTrustZone = false;
137 HasZeroCycleZeroing = false;
138 AllowsUnalignedMem = false;
141 UnsafeFPMath = false;
144 void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
145 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
146 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
148 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
151 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
153 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
155 initializeEnvironment();
156 resetSubtargetFeatures(CPU, FS);
160 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
163 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
164 if (CPUString.empty()) {
165 if (isTargetIOS() && TargetTriple.getArchName().endswith("v7s"))
166 // Default to the Swift CPU when targeting armv7s/thumbv7s.
169 CPUString = "generic";
172 // Insert the architecture feature derived from the target triple into the
173 // feature string. This is important for setting features that are implied
174 // based on the architecture version.
175 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
179 ArchFS = ArchFS + "," + FS.str();
183 ParseSubtargetFeatures(CPUString, ArchFS);
185 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
186 // Assert this for now to make the change obvious.
187 assert(hasV6T2Ops() || !hasThumb2());
189 // Keep a pointer to static instruction cost data for the specified CPU.
190 SchedModel = getSchedModelForCPU(CPUString);
192 // Initialize scheduling itinerary for the specified CPU.
193 InstrItins = getInstrItineraryForCPU(CPUString);
195 if (TargetABI == ARM_ABI_UNKNOWN) {
196 switch (TargetTriple.getEnvironment()) {
197 case Triple::Android:
200 case Triple::GNUEABI:
201 case Triple::GNUEABIHF:
202 TargetABI = ARM_ABI_AAPCS;
205 if ((isTargetIOS() && isMClass()) ||
206 (TargetTriple.isOSBinFormatMachO() &&
207 TargetTriple.getOS() == Triple::UnknownOS))
208 TargetABI = ARM_ABI_AAPCS;
210 TargetABI = ARM_ABI_APCS;
220 UseMovt = hasV6T2Ops() && ArmUseMOVT;
222 if (isTargetMachO()) {
223 IsR9Reserved = ReserveR9 | !HasV6Ops;
224 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
226 IsR9Reserved = ReserveR9;
227 SupportsTailCall = !isThumb1Only();
230 if (!isThumb() || hasThumb2())
231 PostRAScheduler = true;
235 // Assume pre-ARMv6 doesn't support unaligned accesses.
237 // ARMv6 may or may not support unaligned accesses depending on the
238 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
239 // Darwin and NetBSD targets support unaligned accesses, and others don't.
241 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
242 // which raises an alignment fault on unaligned accesses. Linux
243 // defaults this bit to 0 and handles it as a system-wide (not
244 // per-process) setting. It is therefore safe to assume that ARMv7+
245 // Linux targets support unaligned accesses. The same goes for NaCl.
247 // The above behavior is consistent with GCC.
249 (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
250 isTargetNetBSD())) ||
251 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
252 // The one exception is cortex-m0, which despite being v6, does not
253 // support unaligned accesses. Rather than make the above boolean
254 // expression even more obtuse, just override the value here.
255 if (isThumb1Only() && isMClass())
256 AllowsUnalignedMem = false;
259 AllowsUnalignedMem = false;
262 AllowsUnalignedMem = true;
268 RestrictIT = hasV8Ops() ? true : false;
278 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
279 uint64_t Bits = getFeatureBits();
280 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
281 (Options.UnsafeFPMath || isTargetDarwin()))
282 UseNEONForSinglePrecisionFP = true;
285 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
287 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
288 Reloc::Model RelocM) const {
289 if (RelocM == Reloc::Static)
292 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
294 bool isDecl = GV->hasAvailableExternallyLinkage();
295 if (GV->isDeclaration() && !GV->isMaterializable())
298 if (!isTargetMachO()) {
299 // Extra load is needed for all externally visible.
300 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
304 if (RelocM == Reloc::PIC_) {
305 // If this is a strong reference to a definition, it is definitely not
307 if (!isDecl && !GV->isWeakForLinker())
310 // Unless we have a symbol with hidden visibility, we have to go through a
311 // normal $non_lazy_ptr stub because this symbol might be resolved late.
312 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
315 // If symbol visibility is hidden, we have a stub for common symbol
316 // references and external declarations.
317 if (isDecl || GV->hasCommonLinkage())
318 // Hidden $non_lazy_ptr reference.
323 // If this is a strong reference to a definition, it is definitely not
325 if (!isDecl && !GV->isWeakForLinker())
328 // Unless we have a symbol with hidden visibility, we have to go through a
329 // normal $non_lazy_ptr stub because this symbol might be resolved late.
330 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
338 unsigned ARMSubtarget::getMispredictionPenalty() const {
339 return SchedModel->MispredictPenalty;
342 bool ARMSubtarget::hasSinCos() const {
343 return getTargetTriple().getOS() == Triple::IOS &&
344 !getTargetTriple().isOSVersionLT(7, 0);
347 bool ARMSubtarget::enablePostRAScheduler(
348 CodeGenOpt::Level OptLevel,
349 TargetSubtargetInfo::AntiDepBreakMode& Mode,
350 RegClassVector& CriticalPathRCs) const {
351 Mode = TargetSubtargetInfo::ANTIDEP_NONE;
352 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;