1 //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "llvm/Target/TargetInstrItineraries.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetSubtarget.h"
20 #include "ARMBaseRegisterInfo.h"
26 class ARMSubtarget : public TargetSubtarget {
29 V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
32 enum ARMProcFamilyEnum {
33 Others, CortexA8, CortexA9
37 None, VFPv2, VFPv3, NEON
45 /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
46 /// V6, V6T2, V7A, V7M.
47 ARMArchEnum ARMArchVersion;
49 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
50 ARMProcFamilyEnum ARMProcFamily;
52 /// ARMFPUType - Floating Point Unit type.
55 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
56 /// specified. Use the method useNEONForSinglePrecisionFP() to
57 /// determine if NEON should actually be used.
58 bool UseNEONForSinglePrecisionFP;
60 /// SlowVMLx - If the VFP2 instructions are available, indicates whether
61 /// the VML[AS] instructions are slow (if so, don't use them).
64 /// SlowFPBrcc - True if floating point compare + branch is slow.
67 /// IsThumb - True if we are in thumb mode, false if in ARM mode.
70 /// ThumbMode - Indicates supported Thumb version.
71 ThumbTypeEnum ThumbMode;
73 /// NoARM - True if subtarget does not support ARM mode execution.
76 /// PostRAScheduler - True if using post-register-allocation scheduler.
79 /// IsR9Reserved - True if R9 is a not available as general purpose register.
82 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
83 /// imms (including global addresses).
86 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
90 /// HasHardwareDivide - True if subtarget supports [su]div
91 bool HasHardwareDivide;
93 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
95 bool HasT2ExtractPack;
97 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
101 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
102 /// over 16-bit ones.
105 /// FPOnlySP - If true, the floating point unit only supports single
109 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
110 /// accesses for some types. For details, see
111 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
112 bool AllowsUnalignedMem;
114 /// stackAlignment - The minimum alignment known to hold of the stack frame on
115 /// entry to the function and which must be maintained by every function.
116 unsigned stackAlignment;
118 /// CPUString - String name of used CPU.
119 std::string CPUString;
121 /// Selected instruction itineraries (one entry per itinerary class.)
122 InstrItineraryData InstrItins;
131 ARM_ABI_AAPCS // ARM EABI
134 /// This constructor initializes the data members to match that
135 /// of the specified triple.
137 ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
139 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
140 /// that still makes it profitable to inline the call.
141 unsigned getMaxInlineSizeThreshold() const {
142 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
143 // Change this once Thumb1 ldmia / stmia support is added.
144 return isThumb1Only() ? 0 : 64;
146 /// ParseSubtargetFeatures - Parses features string setting specified
147 /// subtarget options. Definition of function is auto generated by tblgen.
148 std::string ParseSubtargetFeatures(const std::string &FS,
149 const std::string &CPU);
151 bool hasV4TOps() const { return ARMArchVersion >= V4T; }
152 bool hasV5TOps() const { return ARMArchVersion >= V5T; }
153 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
154 bool hasV6Ops() const { return ARMArchVersion >= V6; }
155 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
156 bool hasV7Ops() const { return ARMArchVersion >= V7A; }
158 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
159 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
161 bool hasARMOps() const { return !NoARM; }
163 bool hasVFP2() const { return ARMFPUType >= VFPv2; }
164 bool hasVFP3() const { return ARMFPUType >= VFPv3; }
165 bool hasNEON() const { return ARMFPUType >= NEON; }
166 bool useNEONForSinglePrecisionFP() const {
167 return hasNEON() && UseNEONForSinglePrecisionFP; }
168 bool hasDivide() const { return HasHardwareDivide; }
169 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
170 bool hasDataBarrier() const { return HasDataBarrier; }
171 bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
172 bool isFPBrccSlow() const { return SlowFPBrcc; }
173 bool isFPOnlySP() const { return FPOnlySP; }
174 bool prefers32BitThumb() const { return Pref32BitThumb; }
176 bool hasFP16() const { return HasFP16; }
178 bool isTargetDarwin() const { return TargetType == isDarwin; }
179 bool isTargetELF() const { return TargetType == isELF; }
181 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
182 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
184 bool isThumb() const { return IsThumb; }
185 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
186 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
187 bool hasThumb2() const { return ThumbMode >= Thumb2; }
189 bool isR9Reserved() const { return IsR9Reserved; }
191 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
193 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
195 const std::string & getCPUString() const { return CPUString; }
197 unsigned getMispredictionPenalty() const;
199 /// enablePostRAScheduler - True at 'More' optimization.
200 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
201 TargetSubtarget::AntiDepBreakMode& Mode,
202 RegClassVector& CriticalPathRCs) const;
204 /// getInstrItins - Return the instruction itineraies based on subtarget
206 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
208 /// getStackAlignment - Returns the minimum alignment known to hold of the
209 /// stack frame on entry to the function and which must be maintained by every
210 /// function for this subtarget.
211 unsigned getStackAlignment() const { return stackAlignment; }
213 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
215 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
217 /// getDataLayout() - returns the ARM/Thumb specific TargetLayout string
218 std::string getDataLayout() const {
221 return std::string("e-p:32:32-f64:32:64-i64:32:64-"
222 "i16:16:32-i8:8:32-i1:8:32-"
223 "v128:32:128-v64:32:64-a:0:32-n32");
225 return std::string("e-p:32:32-f64:64:64-i64:64:64-"
226 "i16:16:32-i8:8:32-i1:8:32-"
227 "v128:64:128-v64:64:64-a:0:32-n32");
231 return std::string("e-p:32:32-f64:32:64-i64:32:64-"
232 "v128:32:128-v64:32:64-n32");
234 return std::string("e-p:32:32-f64:64:64-i64:64:64-"
235 "v128:64:128-v64:64:64-n32");
240 } // End llvm namespace
242 #endif // ARMSUBTARGET_H