1 //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "llvm/Target/TargetInstrItineraries.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetSubtarget.h"
20 #include "ARMBaseRegisterInfo.h"
26 class ARMSubtarget : public TargetSubtarget {
29 V4T, V5T, V5TE, V6, V6T2, V7A
33 None, VFPv2, VFPv3, NEON
41 /// ARMArchVersion - ARM architecture version: V4T (base), V5T, V5TE,
43 ARMArchEnum ARMArchVersion;
45 /// ARMFPUType - Floating Point Unit type.
48 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
49 /// specified. Use the method useNEONForSinglePrecisionFP() to
50 /// determine if NEON should actually be used.
51 bool UseNEONForSinglePrecisionFP;
53 /// HasBranchTargetBuffer - True if processor can predict indirect branches.
54 bool HasBranchTargetBuffer;
56 /// IsThumb - True if we are in thumb mode, false if in ARM mode.
59 /// ThumbMode - Indicates supported Thumb version.
60 ThumbTypeEnum ThumbMode;
62 /// PostRAScheduler - True if using post-register-allocation scheduler.
65 /// IsR9Reserved - True if R9 is a not available as general purpose register.
68 /// stackAlignment - The minimum alignment known to hold of the stack frame on
69 /// entry to the function and which must be maintained by every function.
70 unsigned stackAlignment;
72 /// CPUString - String name of used CPU.
73 std::string CPUString;
75 /// Selected instruction itineraries (one entry per itinerary class.)
76 InstrItineraryData InstrItins;
85 ARM_ABI_AAPCS // ARM EABI
88 /// This constructor initializes the data members to match that
89 /// of the specified triple.
91 ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
93 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
94 /// that still makes it profitable to inline the call.
95 unsigned getMaxInlineSizeThreshold() const {
96 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb.
97 // Change this once Thumb ldmia / stmia support is added.
98 return isThumb() ? 0 : 64;
100 /// ParseSubtargetFeatures - Parses features string setting specified
101 /// subtarget options. Definition of function is auto generated by tblgen.
102 std::string ParseSubtargetFeatures(const std::string &FS,
103 const std::string &CPU);
105 bool hasV4TOps() const { return ARMArchVersion >= V4T; }
106 bool hasV5TOps() const { return ARMArchVersion >= V5T; }
107 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
108 bool hasV6Ops() const { return ARMArchVersion >= V6; }
109 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
110 bool hasV7Ops() const { return ARMArchVersion >= V7A; }
112 bool hasVFP2() const { return ARMFPUType >= VFPv2; }
113 bool hasVFP3() const { return ARMFPUType >= VFPv3; }
114 bool hasNEON() const { return ARMFPUType >= NEON; }
115 bool useNEONForSinglePrecisionFP() const {
116 return hasNEON() && UseNEONForSinglePrecisionFP; }
118 bool isTargetDarwin() const { return TargetType == isDarwin; }
119 bool isTargetELF() const { return TargetType == isELF; }
121 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
122 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
124 bool isThumb() const { return IsThumb; }
125 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
126 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
127 bool hasThumb2() const { return ThumbMode >= Thumb2; }
129 bool hasBranchTargetBuffer() const { return HasBranchTargetBuffer; }
131 bool isR9Reserved() const { return IsR9Reserved; }
133 const std::string & getCPUString() const { return CPUString; }
135 /// enablePostRAScheduler - True at 'More' optimization.
136 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
137 TargetSubtarget::AntiDepBreakMode& Mode,
138 RegClassVector& CriticalPathRCs) const;
140 /// getInstrItins - Return the instruction itineraies based on subtarget
142 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
144 /// getStackAlignment - Returns the minimum alignment known to hold of the
145 /// stack frame on entry to the function and which must be maintained by every
146 /// function for this subtarget.
147 unsigned getStackAlignment() const { return stackAlignment; }
149 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
151 bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) const;
153 } // End llvm namespace
155 #endif // ARMSUBTARGET_H