1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/Target/TargetSubtargetInfo.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/ADT/Triple.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
30 class ARMSubtarget : public ARMGenSubtargetInfo {
32 enum ARMProcFamilyEnum {
33 Others, CortexA8, CortexA9
36 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
37 ARMProcFamilyEnum ARMProcFamily;
39 /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
40 /// Specify whether target support specific ARM ISA variants.
48 /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON, HasNEONVFPv4 - Specify what
49 /// floating point ISAs are supported.
56 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
57 /// specified. Use the method useNEONForSinglePrecisionFP() to
58 /// determine if NEON should actually be used.
59 bool UseNEONForSinglePrecisionFP;
61 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
62 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
65 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
66 /// forwarding to allow mul + mla being issued back to back.
67 bool HasVMLxForwarding;
69 /// SlowFPBrcc - True if floating point compare + branch is slow.
72 /// InThumbMode - True if compiling for Thumb, false for ARM.
75 /// HasThumb2 - True if Thumb2 instructions are supported.
78 /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
79 /// v6m, v7m for example.
82 /// NoARM - True if subtarget does not support ARM mode execution.
85 /// PostRAScheduler - True if using post-register-allocation scheduler.
88 /// IsR9Reserved - True if R9 is a not available as general purpose register.
91 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
92 /// imms (including global addresses).
95 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
96 /// must be able to synthesize call stubs for interworking between ARM and
98 bool SupportsTailCall;
100 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
104 /// HasD16 - True if subtarget is limited to 16 double precision
105 /// FP registers for VFPv3.
108 /// HasHardwareDivide - True if subtarget supports [su]div
109 bool HasHardwareDivide;
111 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
113 bool HasT2ExtractPack;
115 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
119 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
120 /// over 16-bit ones.
123 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
124 /// that partially update CPSR and add false dependency on the previous
125 /// CPSR setting instruction.
126 bool AvoidCPSRPartialUpdate;
128 /// HasMPExtension - True if the subtarget supports Multiprocessing
129 /// extension (ARMv7 only).
132 /// FPOnlySP - If true, the floating point unit only supports single
136 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
137 /// accesses for some types. For details, see
138 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
139 bool AllowsUnalignedMem;
141 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
142 /// and such) instructions in Thumb2 code.
145 /// stackAlignment - The minimum alignment known to hold of the stack frame on
146 /// entry to the function and which must be maintained by every function.
147 unsigned stackAlignment;
149 /// CPUString - String name of used CPU.
150 std::string CPUString;
152 /// TargetTriple - What processor and OS we're targeting.
155 /// Selected instruction itineraries (one entry per itinerary class.)
156 InstrItineraryData InstrItins;
165 ARM_ABI_AAPCS // ARM EABI
168 /// This constructor initializes the data members to match that
169 /// of the specified triple.
171 ARMSubtarget(const std::string &TT, const std::string &CPU,
172 const std::string &FS);
174 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
175 /// that still makes it profitable to inline the call.
176 unsigned getMaxInlineSizeThreshold() const {
177 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
178 // Change this once Thumb1 ldmia / stmia support is added.
179 return isThumb1Only() ? 0 : 64;
181 /// ParseSubtargetFeatures - Parses features string setting specified
182 /// subtarget options. Definition of function is auto generated by tblgen.
183 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
185 void computeIssueWidth();
187 bool hasV4TOps() const { return HasV4TOps; }
188 bool hasV5TOps() const { return HasV5TOps; }
189 bool hasV5TEOps() const { return HasV5TEOps; }
190 bool hasV6Ops() const { return HasV6Ops; }
191 bool hasV6T2Ops() const { return HasV6T2Ops; }
192 bool hasV7Ops() const { return HasV7Ops; }
194 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
195 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
196 bool isCortexM3() const { return CPUString == "cortex-m3"; }
198 bool hasARMOps() const { return !NoARM; }
200 bool hasVFP2() const { return HasVFPv2; }
201 bool hasVFP3() const { return HasVFPv3; }
202 bool hasVFP4() const { return HasVFPv4; }
203 bool hasNEON() const { return HasNEON; }
204 bool hasNEONVFP4() const { return HasNEONVFPv4; }
205 bool useNEONForSinglePrecisionFP() const {
206 return hasNEON() && UseNEONForSinglePrecisionFP; }
208 bool hasDivide() const { return HasHardwareDivide; }
209 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
210 bool hasDataBarrier() const { return HasDataBarrier; }
211 bool useFPVMLx() const { return !SlowFPVMLx; }
212 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
213 bool isFPBrccSlow() const { return SlowFPBrcc; }
214 bool isFPOnlySP() const { return FPOnlySP; }
215 bool prefers32BitThumb() const { return Pref32BitThumb; }
216 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
217 bool hasMPExtension() const { return HasMPExtension; }
218 bool hasThumb2DSP() const { return Thumb2DSP; }
220 bool hasFP16() const { return HasFP16; }
221 bool hasD16() const { return HasD16; }
223 const Triple &getTargetTriple() const { return TargetTriple; }
225 bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
226 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
227 bool isTargetNaCl() const {
228 return TargetTriple.getOS() == Triple::NativeClient;
230 bool isTargetELF() const { return !isTargetDarwin(); }
232 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
233 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
235 bool isThumb() const { return InThumbMode; }
236 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
237 bool isThumb2() const { return InThumbMode && HasThumb2; }
238 bool hasThumb2() const { return HasThumb2; }
239 bool isMClass() const { return IsMClass; }
240 bool isARClass() const { return !IsMClass; }
242 bool isR9Reserved() const { return IsR9Reserved; }
244 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
245 bool supportsTailCall() const { return SupportsTailCall; }
247 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
249 const std::string & getCPUString() const { return CPUString; }
251 unsigned getMispredictionPenalty() const;
253 /// enablePostRAScheduler - True at 'More' optimization.
254 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
255 TargetSubtargetInfo::AntiDepBreakMode& Mode,
256 RegClassVector& CriticalPathRCs) const;
258 /// getInstrItins - Return the instruction itineraies based on subtarget
260 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
262 /// getStackAlignment - Returns the minimum alignment known to hold of the
263 /// stack frame on entry to the function and which must be maintained by every
264 /// function for this subtarget.
265 unsigned getStackAlignment() const { return stackAlignment; }
267 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
269 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
271 } // End llvm namespace
273 #endif // ARMSUBTARGET_H