1 //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/Target/TargetSubtargetInfo.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/ADT/Triple.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
30 class ARMSubtarget : public ARMGenSubtargetInfo {
32 enum ARMProcFamilyEnum {
33 Others, CortexA8, CortexA9
36 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
37 ARMProcFamilyEnum ARMProcFamily;
39 /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
40 /// Specify whether target support specific ARM ISA variants.
48 /// HasVFPv2, HasVFPv3, HasNEON - Specify what floating point ISAs are
54 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
55 /// specified. Use the method useNEONForSinglePrecisionFP() to
56 /// determine if NEON should actually be used.
57 bool UseNEONForSinglePrecisionFP;
59 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
60 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
63 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
64 /// forwarding to allow mul + mla being issued back to back.
65 bool HasVMLxForwarding;
67 /// SlowFPBrcc - True if floating point compare + branch is slow.
70 /// InThumbMode - True if compiling for Thumb, false for ARM.
73 /// InNaClMode - True if targeting Native Client
76 /// HasThumb2 - True if Thumb2 instructions are supported.
79 /// NoARM - True if subtarget does not support ARM mode execution.
82 /// PostRAScheduler - True if using post-register-allocation scheduler.
85 /// IsR9Reserved - True if R9 is a not available as general purpose register.
88 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
89 /// imms (including global addresses).
92 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
96 /// HasD16 - True if subtarget is limited to 16 double precision
97 /// FP registers for VFPv3.
100 /// HasHardwareDivide - True if subtarget supports [su]div
101 bool HasHardwareDivide;
103 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
105 bool HasT2ExtractPack;
107 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
111 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
112 /// over 16-bit ones.
115 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
116 /// that partially update CPSR and add false dependency on the previous
117 /// CPSR setting instruction.
118 bool AvoidCPSRPartialUpdate;
120 /// HasMPExtension - True if the subtarget supports Multiprocessing
121 /// extension (ARMv7 only).
124 /// FPOnlySP - If true, the floating point unit only supports single
128 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
129 /// accesses for some types. For details, see
130 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
131 bool AllowsUnalignedMem;
133 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
134 /// and such) instructions in Thumb2 code.
137 /// stackAlignment - The minimum alignment known to hold of the stack frame on
138 /// entry to the function and which must be maintained by every function.
139 unsigned stackAlignment;
141 /// CPUString - String name of used CPU.
142 std::string CPUString;
144 /// TargetTriple - What processor and OS we're targeting.
147 /// Selected instruction itineraries (one entry per itinerary class.)
148 InstrItineraryData InstrItins;
157 ARM_ABI_AAPCS // ARM EABI
160 /// This constructor initializes the data members to match that
161 /// of the specified triple.
163 ARMSubtarget(const std::string &TT, const std::string &CPU,
164 const std::string &FS);
166 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
167 /// that still makes it profitable to inline the call.
168 unsigned getMaxInlineSizeThreshold() const {
169 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
170 // Change this once Thumb1 ldmia / stmia support is added.
171 return isThumb1Only() ? 0 : 64;
173 /// ParseSubtargetFeatures - Parses features string setting specified
174 /// subtarget options. Definition of function is auto generated by tblgen.
175 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
177 void computeIssueWidth();
179 bool hasV4TOps() const { return HasV4TOps; }
180 bool hasV5TOps() const { return HasV5TOps; }
181 bool hasV5TEOps() const { return HasV5TEOps; }
182 bool hasV6Ops() const { return HasV6Ops; }
183 bool hasV6T2Ops() const { return HasV6T2Ops; }
184 bool hasV7Ops() const { return HasV7Ops; }
186 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
187 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
189 bool hasARMOps() const { return !NoARM; }
191 bool hasVFP2() const { return HasVFPv2; }
192 bool hasVFP3() const { return HasVFPv3; }
193 bool hasNEON() const { return HasNEON; }
194 bool useNEONForSinglePrecisionFP() const {
195 return hasNEON() && UseNEONForSinglePrecisionFP; }
197 bool hasDivide() const { return HasHardwareDivide; }
198 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
199 bool hasDataBarrier() const { return HasDataBarrier; }
200 bool useFPVMLx() const { return !SlowFPVMLx; }
201 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
202 bool isFPBrccSlow() const { return SlowFPBrcc; }
203 bool isFPOnlySP() const { return FPOnlySP; }
204 bool prefers32BitThumb() const { return Pref32BitThumb; }
205 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
206 bool hasMPExtension() const { return HasMPExtension; }
207 bool hasThumb2DSP() const { return Thumb2DSP; }
209 bool hasFP16() const { return HasFP16; }
210 bool hasD16() const { return HasD16; }
212 const Triple &getTargetTriple() const { return TargetTriple; }
214 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
215 bool isTargetNaCl() const {
216 return TargetTriple.getOS() == Triple::NativeClient;
218 bool isTargetELF() const { return !isTargetDarwin(); }
220 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
221 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
223 bool isThumb() const { return InThumbMode; }
224 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
225 bool isThumb2() const { return InThumbMode && HasThumb2; }
226 bool hasThumb2() const { return HasThumb2; }
228 bool isR9Reserved() const { return IsR9Reserved; }
230 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
232 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
234 const std::string & getCPUString() const { return CPUString; }
236 unsigned getMispredictionPenalty() const;
238 /// enablePostRAScheduler - True at 'More' optimization.
239 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
240 TargetSubtargetInfo::AntiDepBreakMode& Mode,
241 RegClassVector& CriticalPathRCs) const;
243 /// getInstrItins - Return the instruction itineraies based on subtarget
245 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
247 /// getStackAlignment - Returns the minimum alignment known to hold of the
248 /// stack frame on entry to the function and which must be maintained by every
249 /// function for this subtarget.
250 unsigned getStackAlignment() const { return stackAlignment; }
252 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
254 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
256 } // End llvm namespace
258 #endif // ARMSUBTARGET_H