1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
31 class ARMSubtarget : public ARMGenSubtargetInfo {
33 enum ARMProcFamilyEnum {
34 Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift
37 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
38 ARMProcFamilyEnum ARMProcFamily;
40 /// HasV4TOps, HasV5TOps, HasV5TEOps,
41 /// HasV6Ops, HasV6T2Ops, HasV7Ops, HasV8Ops -
42 /// Specify whether target support specific ARM ISA variants.
51 /// HasVFPv2, HasVFPv3, HasVFPv4, HasV8FP, HasNEON - Specify what
52 /// floating point ISAs are supported.
59 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
60 /// specified. Use the method useNEONForSinglePrecisionFP() to
61 /// determine if NEON should actually be used.
62 bool UseNEONForSinglePrecisionFP;
64 /// UseMulOps - True if non-microcoded fused integer multiply-add and
65 /// multiply-subtract instructions should be used.
68 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
69 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
72 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
73 /// forwarding to allow mul + mla being issued back to back.
74 bool HasVMLxForwarding;
76 /// SlowFPBrcc - True if floating point compare + branch is slow.
79 /// InThumbMode - True if compiling for Thumb, false for ARM.
82 /// HasThumb2 - True if Thumb2 instructions are supported.
85 /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
86 /// v6m, v7m for example.
89 /// NoARM - True if subtarget does not support ARM mode execution.
92 /// PostRAScheduler - True if using post-register-allocation scheduler.
95 /// IsR9Reserved - True if R9 is a not available as general purpose register.
98 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
99 /// imms (including global addresses).
102 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
103 /// must be able to synthesize call stubs for interworking between ARM and
105 bool SupportsTailCall;
107 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
111 /// HasD16 - True if subtarget is limited to 16 double precision
112 /// FP registers for VFPv3.
115 /// HasHardwareDivide - True if subtarget supports [su]div
116 bool HasHardwareDivide;
118 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
119 bool HasHardwareDivideInARM;
121 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
123 bool HasT2ExtractPack;
125 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
129 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
130 /// over 16-bit ones.
133 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
134 /// that partially update CPSR and add false dependency on the previous
135 /// CPSR setting instruction.
136 bool AvoidCPSRPartialUpdate;
138 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
139 /// movs with shifter operand (i.e. asr, lsl, lsr).
140 bool AvoidMOVsShifterOperand;
142 /// HasRAS - Some processors perform return stack prediction. CodeGen should
143 /// avoid issue "normal" call instructions to callees which do not return.
146 /// HasMPExtension - True if the subtarget supports Multiprocessing
147 /// extension (ARMv7 only).
150 /// FPOnlySP - If true, the floating point unit only supports single
154 /// If true, the processor supports the Performance Monitor Extensions. These
155 /// include a generic cycle-counter as well as more fine-grained (often
156 /// implementation-specific) events.
159 /// HasTrustZone - if true, processor supports TrustZone security extensions
162 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
163 /// accesses for some types. For details, see
164 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
165 bool AllowsUnalignedMem;
167 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
168 /// and such) instructions in Thumb2 code.
171 /// NaCl TRAP instruction is generated instead of the regular TRAP.
174 /// Target machine allowed unsafe FP math (such as use of NEON fp)
177 /// stackAlignment - The minimum alignment known to hold of the stack frame on
178 /// entry to the function and which must be maintained by every function.
179 unsigned stackAlignment;
181 /// CPUString - String name of used CPU.
182 std::string CPUString;
184 /// TargetTriple - What processor and OS we're targeting.
187 /// SchedModel - Processor specific instruction costs.
188 const MCSchedModel *SchedModel;
190 /// Selected instruction itineraries (one entry per itinerary class.)
191 InstrItineraryData InstrItins;
193 /// Options passed via command line that could influence the target
194 const TargetOptions &Options;
199 ARM_ABI_AAPCS // ARM EABI
202 /// This constructor initializes the data members to match that
203 /// of the specified triple.
205 ARMSubtarget(const std::string &TT, const std::string &CPU,
206 const std::string &FS, const TargetOptions &Options);
208 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
209 /// that still makes it profitable to inline the call.
210 unsigned getMaxInlineSizeThreshold() const {
211 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
212 // Change this once Thumb1 ldmia / stmia support is added.
213 return isThumb1Only() ? 0 : 64;
215 /// ParseSubtargetFeatures - Parses features string setting specified
216 /// subtarget options. Definition of function is auto generated by tblgen.
217 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
219 /// \brief Reset the features for the ARM target.
220 virtual void resetSubtargetFeatures(const MachineFunction *MF);
222 void initializeEnvironment();
223 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
225 void computeIssueWidth();
227 bool hasV4TOps() const { return HasV4TOps; }
228 bool hasV5TOps() const { return HasV5TOps; }
229 bool hasV5TEOps() const { return HasV5TEOps; }
230 bool hasV6Ops() const { return HasV6Ops; }
231 bool hasV6T2Ops() const { return HasV6T2Ops; }
232 bool hasV7Ops() const { return HasV7Ops; }
233 bool hasV8Ops() const { return HasV8Ops; }
235 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
236 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
237 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
238 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
239 bool isSwift() const { return ARMProcFamily == Swift; }
240 bool isCortexM3() const { return CPUString == "cortex-m3"; }
241 bool isLikeA9() const { return isCortexA9() || isCortexA15(); }
242 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
244 bool hasARMOps() const { return !NoARM; }
246 bool hasVFP2() const { return HasVFPv2; }
247 bool hasVFP3() const { return HasVFPv3; }
248 bool hasVFP4() const { return HasVFPv4; }
249 bool hasV8FP() const { return HasV8FP; }
250 bool hasNEON() const { return HasNEON; }
251 bool useNEONForSinglePrecisionFP() const {
252 return hasNEON() && UseNEONForSinglePrecisionFP; }
254 bool hasDivide() const { return HasHardwareDivide; }
255 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
256 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
257 bool hasDataBarrier() const { return HasDataBarrier; }
258 bool useMulOps() const { return UseMulOps; }
259 bool useFPVMLx() const { return !SlowFPVMLx; }
260 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
261 bool isFPBrccSlow() const { return SlowFPBrcc; }
262 bool isFPOnlySP() const { return FPOnlySP; }
263 bool hasPerfMon() const { return HasPerfMon; }
264 bool hasTrustZone() const { return HasTrustZone; }
265 bool prefers32BitThumb() const { return Pref32BitThumb; }
266 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
267 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
268 bool hasRAS() const { return HasRAS; }
269 bool hasMPExtension() const { return HasMPExtension; }
270 bool hasThumb2DSP() const { return Thumb2DSP; }
271 bool useNaClTrap() const { return UseNaClTrap; }
273 bool hasFP16() const { return HasFP16; }
274 bool hasD16() const { return HasD16; }
276 const Triple &getTargetTriple() const { return TargetTriple; }
278 bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
279 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
280 bool isTargetNaCl() const { return TargetTriple.getOS() == Triple::NaCl; }
281 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
282 bool isTargetELF() const { return !isTargetDarwin(); }
283 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
284 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
285 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
286 // even for GNUEABI, so we can make a distinction here and still conform to
287 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
288 bool isTargetAEABI() const {
289 return TargetTriple.getEnvironment() == Triple::EABI;
292 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
293 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
295 bool isThumb() const { return InThumbMode; }
296 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
297 bool isThumb2() const { return InThumbMode && HasThumb2; }
298 bool hasThumb2() const { return HasThumb2; }
299 bool isMClass() const { return IsMClass; }
300 bool isARClass() const { return !IsMClass; }
302 bool isR9Reserved() const { return IsR9Reserved; }
304 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
305 bool supportsTailCall() const { return SupportsTailCall; }
307 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
309 const std::string & getCPUString() const { return CPUString; }
311 unsigned getMispredictionPenalty() const;
313 /// enablePostRAScheduler - True at 'More' optimization.
314 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
315 TargetSubtargetInfo::AntiDepBreakMode& Mode,
316 RegClassVector& CriticalPathRCs) const;
318 /// getInstrItins - Return the instruction itineraies based on subtarget
320 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
322 /// getStackAlignment - Returns the minimum alignment known to hold of the
323 /// stack frame on entry to the function and which must be maintained by every
324 /// function for this subtarget.
325 unsigned getStackAlignment() const { return stackAlignment; }
327 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
329 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
331 } // End llvm namespace
333 #endif // ARMSUBTARGET_H