1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
18 #include "ARMFrameLowering.h"
19 #include "ARMISelLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMMCTargetDesc.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/MC/MCInstrItineraries.h"
30 #include "llvm/Target/TargetSubtargetInfo.h"
33 #define GET_SUBTARGETINFO_HEADER
34 #include "ARMGenSubtargetInfo.inc"
40 class ARMBaseTargetMachine;
42 class ARMSubtarget : public ARMGenSubtargetInfo {
44 enum ARMProcFamilyEnum {
45 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
46 CortexA17, CortexR5, Swift, CortexA53, CortexA57, Krait,
48 enum ARMProcClassEnum {
49 None, AClass, RClass, MClass
52 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
53 ARMProcFamilyEnum ARMProcFamily;
55 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
56 ARMProcClassEnum ARMProcClass;
58 /// HasV4TOps, HasV5TOps, HasV5TEOps,
59 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
60 /// Specify whether target support specific ARM ISA variants.
72 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
73 /// floating point ISAs are supported.
80 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
81 /// specified. Use the method useNEONForSinglePrecisionFP() to
82 /// determine if NEON should actually be used.
83 bool UseNEONForSinglePrecisionFP;
85 /// UseMulOps - True if non-microcoded fused integer multiply-add and
86 /// multiply-subtract instructions should be used.
89 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
90 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
93 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
94 /// forwarding to allow mul + mla being issued back to back.
95 bool HasVMLxForwarding;
97 /// SlowFPBrcc - True if floating point compare + branch is slow.
100 /// InThumbMode - True if compiling for Thumb, false for ARM.
103 /// HasThumb2 - True if Thumb2 instructions are supported.
106 /// NoARM - True if subtarget does not support ARM mode execution.
109 /// IsR9Reserved - True if R9 is a not available as general purpose register.
112 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
113 /// imms (including global addresses).
116 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
117 /// must be able to synthesize call stubs for interworking between ARM and
119 bool SupportsTailCall;
121 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
125 /// HasD16 - True if subtarget is limited to 16 double precision
126 /// FP registers for VFPv3.
129 /// HasHardwareDivide - True if subtarget supports [su]div
130 bool HasHardwareDivide;
132 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
133 bool HasHardwareDivideInARM;
135 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
137 bool HasT2ExtractPack;
139 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
143 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
144 /// over 16-bit ones.
147 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
148 /// that partially update CPSR and add false dependency on the previous
149 /// CPSR setting instruction.
150 bool AvoidCPSRPartialUpdate;
152 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
153 /// movs with shifter operand (i.e. asr, lsl, lsr).
154 bool AvoidMOVsShifterOperand;
156 /// HasRAS - Some processors perform return stack prediction. CodeGen should
157 /// avoid issue "normal" call instructions to callees which do not return.
160 /// HasMPExtension - True if the subtarget supports Multiprocessing
161 /// extension (ARMv7 only).
164 /// HasVirtualization - True if the subtarget supports the Virtualization
166 bool HasVirtualization;
168 /// FPOnlySP - If true, the floating point unit only supports single
172 /// If true, the processor supports the Performance Monitor Extensions. These
173 /// include a generic cycle-counter as well as more fine-grained (often
174 /// implementation-specific) events.
177 /// HasTrustZone - if true, processor supports TrustZone security extensions
180 /// HasCrypto - if true, processor supports Cryptography extensions
183 /// HasCRC - if true, processor supports CRC instructions
186 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
187 /// particularly effective at zeroing a VFP register.
188 bool HasZeroCycleZeroing;
190 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
191 /// accesses for some types. For details, see
192 /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
193 bool AllowsUnalignedMem;
195 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
196 /// blocks to conform to ARMv8 rule.
199 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
200 /// and such) instructions in Thumb2 code.
203 /// NaCl TRAP instruction is generated instead of the regular TRAP.
206 /// Target machine allowed unsafe FP math (such as use of NEON fp)
209 /// stackAlignment - The minimum alignment known to hold of the stack frame on
210 /// entry to the function and which must be maintained by every function.
211 unsigned stackAlignment;
213 /// CPUString - String name of used CPU.
214 std::string CPUString;
216 /// IsLittle - The target is Little Endian
219 /// TargetTriple - What processor and OS we're targeting.
222 /// SchedModel - Processor specific instruction costs.
223 MCSchedModel SchedModel;
225 /// Selected instruction itineraries (one entry per itinerary class.)
226 InstrItineraryData InstrItins;
228 /// Options passed via command line that could influence the target
229 const TargetOptions &Options;
231 const ARMBaseTargetMachine &TM;
234 /// This constructor initializes the data members to match that
235 /// of the specified triple.
237 ARMSubtarget(const std::string &TT, const std::string &CPU,
238 const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle);
240 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
241 /// that still makes it profitable to inline the call.
242 unsigned getMaxInlineSizeThreshold() const {
245 /// ParseSubtargetFeatures - Parses features string setting specified
246 /// subtarget options. Definition of function is auto generated by tblgen.
247 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
249 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
250 /// so that we can use initializer lists for subtarget initialization.
251 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
253 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
256 const ARMBaseInstrInfo *getInstrInfo() const override {
257 return InstrInfo.get();
259 const ARMTargetLowering *getTargetLowering() const override {
262 const ARMFrameLowering *getFrameLowering() const override {
263 return FrameLowering.get();
265 const ARMBaseRegisterInfo *getRegisterInfo() const override {
266 return &InstrInfo->getRegisterInfo();
270 ARMSelectionDAGInfo TSInfo;
271 // Either Thumb1FrameLowering or ARMFrameLowering.
272 std::unique_ptr<ARMFrameLowering> FrameLowering;
273 // Either Thumb1InstrInfo or Thumb2InstrInfo.
274 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
275 ARMTargetLowering TLInfo;
277 void initializeEnvironment();
278 void initSubtargetFeatures(StringRef CPU, StringRef FS);
279 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
282 void computeIssueWidth();
284 bool hasV4TOps() const { return HasV4TOps; }
285 bool hasV5TOps() const { return HasV5TOps; }
286 bool hasV5TEOps() const { return HasV5TEOps; }
287 bool hasV6Ops() const { return HasV6Ops; }
288 bool hasV6MOps() const { return HasV6MOps; }
289 bool hasV6KOps() const { return HasV6KOps; }
290 bool hasV6T2Ops() const { return HasV6T2Ops; }
291 bool hasV7Ops() const { return HasV7Ops; }
292 bool hasV8Ops() const { return HasV8Ops; }
293 bool hasV8_1aOps() const { return HasV8_1aOps; }
295 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
296 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
297 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
298 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
299 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
300 bool isSwift() const { return ARMProcFamily == Swift; }
301 bool isCortexM3() const { return CPUString == "cortex-m3"; }
302 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
303 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
304 bool isKrait() const { return ARMProcFamily == Krait; }
306 bool hasARMOps() const { return !NoARM; }
308 bool hasVFP2() const { return HasVFPv2; }
309 bool hasVFP3() const { return HasVFPv3; }
310 bool hasVFP4() const { return HasVFPv4; }
311 bool hasFPARMv8() const { return HasFPARMv8; }
312 bool hasNEON() const { return HasNEON; }
313 bool hasCrypto() const { return HasCrypto; }
314 bool hasCRC() const { return HasCRC; }
315 bool hasVirtualization() const { return HasVirtualization; }
316 bool useNEONForSinglePrecisionFP() const {
317 return hasNEON() && UseNEONForSinglePrecisionFP;
320 bool hasDivide() const { return HasHardwareDivide; }
321 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
322 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
323 bool hasDataBarrier() const { return HasDataBarrier; }
324 bool hasAnyDataBarrier() const {
325 return HasDataBarrier || (hasV6Ops() && !isThumb());
327 bool useMulOps() const { return UseMulOps; }
328 bool useFPVMLx() const { return !SlowFPVMLx; }
329 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
330 bool isFPBrccSlow() const { return SlowFPBrcc; }
331 bool isFPOnlySP() const { return FPOnlySP; }
332 bool hasPerfMon() const { return HasPerfMon; }
333 bool hasTrustZone() const { return HasTrustZone; }
334 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
335 bool prefers32BitThumb() const { return Pref32BitThumb; }
336 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
337 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
338 bool hasRAS() const { return HasRAS; }
339 bool hasMPExtension() const { return HasMPExtension; }
340 bool hasThumb2DSP() const { return Thumb2DSP; }
341 bool useNaClTrap() const { return UseNaClTrap; }
343 bool hasFP16() const { return HasFP16; }
344 bool hasD16() const { return HasD16; }
346 const Triple &getTargetTriple() const { return TargetTriple; }
348 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
349 bool isTargetIOS() const { return TargetTriple.isiOS(); }
350 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
351 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
352 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
353 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
355 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
356 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
357 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
359 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
360 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
361 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
362 // even for GNUEABI, so we can make a distinction here and still conform to
363 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
364 // FIXME: The Darwin exception is temporary, while we move users to
365 // "*-*-*-macho" triples as quickly as possible.
366 bool isTargetAEABI() const {
367 return (TargetTriple.getEnvironment() == Triple::EABI ||
368 TargetTriple.getEnvironment() == Triple::EABIHF) &&
369 !isTargetDarwin() && !isTargetWindows();
372 // ARM Targets that support EHABI exception handling standard
373 // Darwin uses SjLj. Other targets might need more checks.
374 bool isTargetEHABICompatible() const {
375 return (TargetTriple.getEnvironment() == Triple::EABI ||
376 TargetTriple.getEnvironment() == Triple::GNUEABI ||
377 TargetTriple.getEnvironment() == Triple::EABIHF ||
378 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
379 TargetTriple.getEnvironment() == Triple::Android) &&
380 !isTargetDarwin() && !isTargetWindows();
383 bool isTargetHardFloat() const {
384 // FIXME: this is invalid for WindowsCE
385 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
386 TargetTriple.getEnvironment() == Triple::EABIHF ||
389 bool isTargetAndroid() const {
390 return TargetTriple.getEnvironment() == Triple::Android;
393 bool isAPCS_ABI() const;
394 bool isAAPCS_ABI() const;
396 bool isThumb() const { return InThumbMode; }
397 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
398 bool isThumb2() const { return InThumbMode && HasThumb2; }
399 bool hasThumb2() const { return HasThumb2; }
400 bool isMClass() const { return ARMProcClass == MClass; }
401 bool isRClass() const { return ARMProcClass == RClass; }
402 bool isAClass() const { return ARMProcClass == AClass; }
405 return isThumb1Only() && isMClass();
408 bool isR9Reserved() const { return IsR9Reserved; }
410 bool useMovt(const MachineFunction &MF) const;
412 bool supportsTailCall() const { return SupportsTailCall; }
414 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
416 bool restrictIT() const { return RestrictIT; }
418 const std::string & getCPUString() const { return CPUString; }
420 bool isLittle() const { return IsLittle; }
422 unsigned getMispredictionPenalty() const;
424 /// This function returns true if the target has sincos() routine in its
425 /// compiler runtime or math libraries.
426 bool hasSinCos() const;
428 /// True for some subtargets at > -O0.
429 bool enablePostMachineScheduler() const override;
431 // enableAtomicExpand- True if we need to expand our atomics.
432 bool enableAtomicExpand() const override;
434 /// getInstrItins - Return the instruction itineraries based on subtarget
436 const InstrItineraryData *getInstrItineraryData() const override {
440 /// getStackAlignment - Returns the minimum alignment known to hold of the
441 /// stack frame on entry to the function and which must be maintained by every
442 /// function for this subtarget.
443 unsigned getStackAlignment() const { return stackAlignment; }
445 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
447 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
450 } // End llvm namespace
452 #endif // ARMSUBTARGET_H