1 //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "llvm/Target/TargetInstrItineraries.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetSubtarget.h"
20 #include "ARMBaseRegisterInfo.h"
26 class ARMSubtarget : public TargetSubtarget {
29 V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
33 None, VFPv2, VFPv3, NEON
41 /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
42 /// V6, V6T2, V7A, V7M.
43 ARMArchEnum ARMArchVersion;
45 /// ARMFPUType - Floating Point Unit type.
48 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
49 /// specified. Use the method useNEONForSinglePrecisionFP() to
50 /// determine if NEON should actually be used.
51 bool UseNEONForSinglePrecisionFP;
53 /// SlowVMLx - If the VFP2 instructions are available, indicates whether
54 /// the VML[AS] instructions are slow (if so, don't use them).
57 /// SlowFPBrcc - True if floating point compare + branch is slow.
60 /// IsThumb - True if we are in thumb mode, false if in ARM mode.
63 /// ThumbMode - Indicates supported Thumb version.
64 ThumbTypeEnum ThumbMode;
66 /// PostRAScheduler - True if using post-register-allocation scheduler.
69 /// IsR9Reserved - True if R9 is a not available as general purpose register.
72 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
73 /// imms (including global addresses).
76 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
80 /// HasHardwareDivide - True if subtarget supports [su]div
81 bool HasHardwareDivide;
83 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
85 bool HasT2ExtractPack;
87 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
91 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
95 /// stackAlignment - The minimum alignment known to hold of the stack frame on
96 /// entry to the function and which must be maintained by every function.
97 unsigned stackAlignment;
99 /// CPUString - String name of used CPU.
100 std::string CPUString;
102 /// Selected instruction itineraries (one entry per itinerary class.)
103 InstrItineraryData InstrItins;
112 ARM_ABI_AAPCS // ARM EABI
115 /// This constructor initializes the data members to match that
116 /// of the specified triple.
118 ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
120 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
121 /// that still makes it profitable to inline the call.
122 unsigned getMaxInlineSizeThreshold() const {
123 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
124 // Change this once Thumb1 ldmia / stmia support is added.
125 return isThumb1Only() ? 0 : 64;
127 /// ParseSubtargetFeatures - Parses features string setting specified
128 /// subtarget options. Definition of function is auto generated by tblgen.
129 std::string ParseSubtargetFeatures(const std::string &FS,
130 const std::string &CPU);
132 bool hasV4TOps() const { return ARMArchVersion >= V4T; }
133 bool hasV5TOps() const { return ARMArchVersion >= V5T; }
134 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
135 bool hasV6Ops() const { return ARMArchVersion >= V6; }
136 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
137 bool hasV7Ops() const { return ARMArchVersion >= V7A; }
139 bool hasVFP2() const { return ARMFPUType >= VFPv2; }
140 bool hasVFP3() const { return ARMFPUType >= VFPv3; }
141 bool hasNEON() const { return ARMFPUType >= NEON; }
142 bool useNEONForSinglePrecisionFP() const {
143 return hasNEON() && UseNEONForSinglePrecisionFP; }
144 bool hasDivide() const { return HasHardwareDivide; }
145 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
146 bool hasDataBarrier() const { return HasDataBarrier; }
147 bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
148 bool isFPBrccSlow() const { return SlowFPBrcc; }
149 bool prefers32BitThumb() const { return Pref32BitThumb; }
151 bool hasFP16() const { return HasFP16; }
153 bool isTargetDarwin() const { return TargetType == isDarwin; }
154 bool isTargetELF() const { return TargetType == isELF; }
156 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
157 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
159 bool isThumb() const { return IsThumb; }
160 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
161 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
162 bool hasThumb2() const { return ThumbMode >= Thumb2; }
164 bool isR9Reserved() const { return IsR9Reserved; }
166 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
168 const std::string & getCPUString() const { return CPUString; }
170 /// enablePostRAScheduler - True at 'More' optimization.
171 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
172 TargetSubtarget::AntiDepBreakMode& Mode,
173 RegClassVector& CriticalPathRCs) const;
175 /// getInstrItins - Return the instruction itineraies based on subtarget
177 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
179 /// getStackAlignment - Returns the minimum alignment known to hold of the
180 /// stack frame on entry to the function and which must be maintained by every
181 /// function for this subtarget.
182 unsigned getStackAlignment() const { return stackAlignment; }
184 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
186 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
188 } // End llvm namespace
190 #endif // ARMSUBTARGET_H