1 //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "llvm/Target/TargetInstrItineraries.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetSubtarget.h"
20 #include "ARMBaseRegisterInfo.h"
26 class ARMSubtarget : public TargetSubtarget {
29 V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
32 enum ARMProcFamilyEnum {
33 Others, CortexA8, CortexA9
37 None, VFPv2, VFPv3, NEON
45 /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
46 /// V6, V6T2, V7A, V7M.
47 ARMArchEnum ARMArchVersion;
49 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
50 ARMProcFamilyEnum ARMProcFamily;
52 /// ARMFPUType - Floating Point Unit type.
55 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
56 /// specified. Use the method useNEONForSinglePrecisionFP() to
57 /// determine if NEON should actually be used.
58 bool UseNEONForSinglePrecisionFP;
60 /// SlowVMLx - If the VFP2 instructions are available, indicates whether
61 /// the VML[AS] instructions are slow (if so, don't use them).
64 /// SlowFPBrcc - True if floating point compare + branch is slow.
67 /// IsThumb - True if we are in thumb mode, false if in ARM mode.
70 /// ThumbMode - Indicates supported Thumb version.
71 ThumbTypeEnum ThumbMode;
73 /// NoARM - True if subtarget does not support ARM mode execution.
76 /// PostRAScheduler - True if using post-register-allocation scheduler.
79 /// IsR9Reserved - True if R9 is a not available as general purpose register.
82 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
83 /// imms (including global addresses).
86 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
90 /// HasD16 - True if subtarget is limited to 16 double precision
91 /// FP registers for VFPv3.
94 /// HasHardwareDivide - True if subtarget supports [su]div
95 bool HasHardwareDivide;
97 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
99 bool HasT2ExtractPack;
101 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
105 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
106 /// over 16-bit ones.
109 /// FPOnlySP - If true, the floating point unit only supports single
113 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
114 /// accesses for some types. For details, see
115 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
116 bool AllowsUnalignedMem;
118 /// stackAlignment - The minimum alignment known to hold of the stack frame on
119 /// entry to the function and which must be maintained by every function.
120 unsigned stackAlignment;
122 /// CPUString - String name of used CPU.
123 std::string CPUString;
125 /// Selected instruction itineraries (one entry per itinerary class.)
126 InstrItineraryData InstrItins;
135 ARM_ABI_AAPCS // ARM EABI
138 /// This constructor initializes the data members to match that
139 /// of the specified triple.
141 ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
143 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
144 /// that still makes it profitable to inline the call.
145 unsigned getMaxInlineSizeThreshold() const {
146 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
147 // Change this once Thumb1 ldmia / stmia support is added.
148 return isThumb1Only() ? 0 : 64;
150 /// ParseSubtargetFeatures - Parses features string setting specified
151 /// subtarget options. Definition of function is auto generated by tblgen.
152 std::string ParseSubtargetFeatures(const std::string &FS,
153 const std::string &CPU);
155 bool hasV4TOps() const { return ARMArchVersion >= V4T; }
156 bool hasV5TOps() const { return ARMArchVersion >= V5T; }
157 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
158 bool hasV6Ops() const { return ARMArchVersion >= V6; }
159 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
160 bool hasV7Ops() const { return ARMArchVersion >= V7A; }
162 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
163 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
165 bool hasARMOps() const { return !NoARM; }
167 bool hasVFP2() const { return ARMFPUType >= VFPv2; }
168 bool hasVFP3() const { return ARMFPUType >= VFPv3; }
169 bool hasNEON() const { return ARMFPUType >= NEON; }
170 bool useNEONForSinglePrecisionFP() const {
171 return hasNEON() && UseNEONForSinglePrecisionFP; }
172 bool hasDivide() const { return HasHardwareDivide; }
173 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
174 bool hasDataBarrier() const { return HasDataBarrier; }
175 bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
176 bool isFPBrccSlow() const { return SlowFPBrcc; }
177 bool isFPOnlySP() const { return FPOnlySP; }
178 bool prefers32BitThumb() const { return Pref32BitThumb; }
180 bool hasFP16() const { return HasFP16; }
181 bool hasD16() const { return HasD16; }
183 bool isTargetDarwin() const { return TargetType == isDarwin; }
184 bool isTargetELF() const { return TargetType == isELF; }
186 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
187 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
189 bool isThumb() const { return IsThumb; }
190 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
191 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
192 bool hasThumb2() const { return ThumbMode >= Thumb2; }
194 bool isR9Reserved() const { return IsR9Reserved; }
196 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
198 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
200 const std::string & getCPUString() const { return CPUString; }
202 unsigned getMispredictionPenalty() const;
204 /// enablePostRAScheduler - True at 'More' optimization.
205 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
206 TargetSubtarget::AntiDepBreakMode& Mode,
207 RegClassVector& CriticalPathRCs) const;
209 /// getInstrItins - Return the instruction itineraies based on subtarget
211 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
213 /// getStackAlignment - Returns the minimum alignment known to hold of the
214 /// stack frame on entry to the function and which must be maintained by every
215 /// function for this subtarget.
216 unsigned getStackAlignment() const { return stackAlignment; }
218 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
220 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
222 } // End llvm namespace
224 #endif // ARMSUBTARGET_H