1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
31 class ARMSubtarget : public ARMGenSubtargetInfo {
33 enum ARMProcFamilyEnum {
34 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
35 CortexR5, Swift, CortexA53, CortexA57, Krait
37 enum ARMProcClassEnum {
38 None, AClass, RClass, MClass
41 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
42 ARMProcFamilyEnum ARMProcFamily;
44 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
45 ARMProcClassEnum ARMProcClass;
47 /// HasV4TOps, HasV5TOps, HasV5TEOps,
48 /// HasV6Ops, HasV6MOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
49 /// Specify whether target support specific ARM ISA variants.
59 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
60 /// floating point ISAs are supported.
67 /// MinSize - True if the function being compiled has the "minsize" attribute
68 /// and should be optimised for size at the expense of speed.
71 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
72 /// specified. Use the method useNEONForSinglePrecisionFP() to
73 /// determine if NEON should actually be used.
74 bool UseNEONForSinglePrecisionFP;
76 /// UseMulOps - True if non-microcoded fused integer multiply-add and
77 /// multiply-subtract instructions should be used.
80 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
81 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
84 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
85 /// forwarding to allow mul + mla being issued back to back.
86 bool HasVMLxForwarding;
88 /// SlowFPBrcc - True if floating point compare + branch is slow.
91 /// InThumbMode - True if compiling for Thumb, false for ARM.
94 /// HasThumb2 - True if Thumb2 instructions are supported.
97 /// NoARM - True if subtarget does not support ARM mode execution.
100 /// PostRAScheduler - True if using post-register-allocation scheduler.
101 bool PostRAScheduler;
103 /// IsR9Reserved - True if R9 is a not available as general purpose register.
106 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
107 /// imms (including global addresses).
110 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
111 /// must be able to synthesize call stubs for interworking between ARM and
113 bool SupportsTailCall;
115 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
119 /// HasD16 - True if subtarget is limited to 16 double precision
120 /// FP registers for VFPv3.
123 /// HasHardwareDivide - True if subtarget supports [su]div
124 bool HasHardwareDivide;
126 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
127 bool HasHardwareDivideInARM;
129 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
131 bool HasT2ExtractPack;
133 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
137 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
138 /// over 16-bit ones.
141 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
142 /// that partially update CPSR and add false dependency on the previous
143 /// CPSR setting instruction.
144 bool AvoidCPSRPartialUpdate;
146 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
147 /// movs with shifter operand (i.e. asr, lsl, lsr).
148 bool AvoidMOVsShifterOperand;
150 /// HasRAS - Some processors perform return stack prediction. CodeGen should
151 /// avoid issue "normal" call instructions to callees which do not return.
154 /// HasMPExtension - True if the subtarget supports Multiprocessing
155 /// extension (ARMv7 only).
158 /// HasVirtualization - True if the subtarget supports the Virtualization
160 bool HasVirtualization;
162 /// FPOnlySP - If true, the floating point unit only supports single
166 /// If true, the processor supports the Performance Monitor Extensions. These
167 /// include a generic cycle-counter as well as more fine-grained (often
168 /// implementation-specific) events.
171 /// HasTrustZone - if true, processor supports TrustZone security extensions
174 /// HasCrypto - if true, processor supports Cryptography extensions
177 /// HasCRC - if true, processor supports CRC instructions
180 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
181 /// accesses for some types. For details, see
182 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
183 bool AllowsUnalignedMem;
185 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
186 /// blocks to conform to ARMv8 rule.
189 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
190 /// and such) instructions in Thumb2 code.
193 /// NaCl TRAP instruction is generated instead of the regular TRAP.
196 /// Target machine allowed unsafe FP math (such as use of NEON fp)
199 /// stackAlignment - The minimum alignment known to hold of the stack frame on
200 /// entry to the function and which must be maintained by every function.
201 unsigned stackAlignment;
203 /// CPUString - String name of used CPU.
204 std::string CPUString;
206 /// TargetTriple - What processor and OS we're targeting.
209 /// SchedModel - Processor specific instruction costs.
210 const MCSchedModel *SchedModel;
212 /// Selected instruction itineraries (one entry per itinerary class.)
213 InstrItineraryData InstrItins;
215 /// Options passed via command line that could influence the target
216 const TargetOptions &Options;
222 ARM_ABI_AAPCS // ARM EABI
225 /// This constructor initializes the data members to match that
226 /// of the specified triple.
228 ARMSubtarget(const std::string &TT, const std::string &CPU,
229 const std::string &FS, const TargetOptions &Options);
231 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
232 /// that still makes it profitable to inline the call.
233 unsigned getMaxInlineSizeThreshold() const {
234 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
235 // Change this once Thumb1 ldmia / stmia support is added.
236 return isThumb1Only() ? 0 : 64;
238 /// ParseSubtargetFeatures - Parses features string setting specified
239 /// subtarget options. Definition of function is auto generated by tblgen.
240 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
242 /// \brief Reset the features for the ARM target.
243 virtual void resetSubtargetFeatures(const MachineFunction *MF);
245 void initializeEnvironment();
246 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
248 void computeIssueWidth();
250 bool hasV4TOps() const { return HasV4TOps; }
251 bool hasV5TOps() const { return HasV5TOps; }
252 bool hasV5TEOps() const { return HasV5TEOps; }
253 bool hasV6Ops() const { return HasV6Ops; }
254 bool hasV6MOps() const { return HasV6MOps; }
255 bool hasV6T2Ops() const { return HasV6T2Ops; }
256 bool hasV7Ops() const { return HasV7Ops; }
257 bool hasV8Ops() const { return HasV8Ops; }
259 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
260 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
261 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
262 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
263 bool isSwift() const { return ARMProcFamily == Swift; }
264 bool isCortexM3() const { return CPUString == "cortex-m3"; }
265 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
266 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
267 bool isKrait() const { return ARMProcFamily == Krait; }
269 bool hasARMOps() const { return !NoARM; }
271 bool hasVFP2() const { return HasVFPv2; }
272 bool hasVFP3() const { return HasVFPv3; }
273 bool hasVFP4() const { return HasVFPv4; }
274 bool hasFPARMv8() const { return HasFPARMv8; }
275 bool hasNEON() const { return HasNEON; }
276 bool hasCrypto() const { return HasCrypto; }
277 bool hasCRC() const { return HasCRC; }
278 bool hasVirtualization() const { return HasVirtualization; }
279 bool isMinSize() const { return MinSize; }
280 bool useNEONForSinglePrecisionFP() const {
281 return hasNEON() && UseNEONForSinglePrecisionFP; }
283 bool hasDivide() const { return HasHardwareDivide; }
284 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
285 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
286 bool hasDataBarrier() const { return HasDataBarrier; }
287 bool hasAnyDataBarrier() const {
288 return HasDataBarrier || (hasV6Ops() && !isThumb());
290 bool useMulOps() const { return UseMulOps; }
291 bool useFPVMLx() const { return !SlowFPVMLx; }
292 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
293 bool isFPBrccSlow() const { return SlowFPBrcc; }
294 bool isFPOnlySP() const { return FPOnlySP; }
295 bool hasPerfMon() const { return HasPerfMon; }
296 bool hasTrustZone() const { return HasTrustZone; }
297 bool prefers32BitThumb() const { return Pref32BitThumb; }
298 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
299 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
300 bool hasRAS() const { return HasRAS; }
301 bool hasMPExtension() const { return HasMPExtension; }
302 bool hasThumb2DSP() const { return Thumb2DSP; }
303 bool useNaClTrap() const { return UseNaClTrap; }
305 bool hasFP16() const { return HasFP16; }
306 bool hasD16() const { return HasD16; }
308 const Triple &getTargetTriple() const { return TargetTriple; }
310 bool isTargetIOS() const { return TargetTriple.isiOS(); }
311 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
312 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
313 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
314 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
315 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
316 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
317 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
318 // even for GNUEABI, so we can make a distinction here and still conform to
319 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
320 // FIXME: The Darwin exception is temporary, while we move users to
321 // "*-*-*-macho" triples as quickly as possible.
322 bool isTargetAEABI() const {
323 return (TargetTriple.getEnvironment() == Triple::EABI ||
324 TargetTriple.getEnvironment() == Triple::EABIHF) &&
328 bool isTargetHardFloat() const {
329 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
330 TargetTriple.getEnvironment() == Triple::EABIHF;
333 bool isAPCS_ABI() const {
334 assert(TargetABI != ARM_ABI_UNKNOWN);
335 return TargetABI == ARM_ABI_APCS;
337 bool isAAPCS_ABI() const {
338 assert(TargetABI != ARM_ABI_UNKNOWN);
339 return TargetABI == ARM_ABI_AAPCS;
342 bool isThumb() const { return InThumbMode; }
343 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
344 bool isThumb2() const { return InThumbMode && HasThumb2; }
345 bool hasThumb2() const { return HasThumb2; }
346 bool isMClass() const { return ARMProcClass == MClass; }
347 bool isRClass() const { return ARMProcClass == RClass; }
348 bool isAClass() const { return ARMProcClass == AClass; }
350 bool isR9Reserved() const { return IsR9Reserved; }
352 bool useMovt() const { return UseMovt && !isMinSize(); }
353 bool supportsTailCall() const { return SupportsTailCall; }
355 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
357 bool restrictIT() const { return RestrictIT; }
359 const std::string & getCPUString() const { return CPUString; }
361 unsigned getMispredictionPenalty() const;
363 /// This function returns true if the target has sincos() routine in its
364 /// compiler runtime or math libraries.
365 bool hasSinCos() const;
367 /// enablePostRAScheduler - True at 'More' optimization.
368 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
369 TargetSubtargetInfo::AntiDepBreakMode& Mode,
370 RegClassVector& CriticalPathRCs) const;
372 /// getInstrItins - Return the instruction itineraies based on subtarget
374 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
376 /// getStackAlignment - Returns the minimum alignment known to hold of the
377 /// stack frame on entry to the function and which must be maintained by every
378 /// function for this subtarget.
379 unsigned getStackAlignment() const { return stackAlignment; }
381 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
383 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
385 } // End llvm namespace
387 #endif // ARMSUBTARGET_H