1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/Target/TargetSubtargetInfo.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/ADT/Triple.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
30 class ARMSubtarget : public ARMGenSubtargetInfo {
32 enum ARMProcFamilyEnum {
33 Others, CortexA8, CortexA9
36 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
37 ARMProcFamilyEnum ARMProcFamily;
39 /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
40 /// Specify whether target support specific ARM ISA variants.
48 /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what
49 /// floating point ISAs are supported.
55 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
56 /// specified. Use the method useNEONForSinglePrecisionFP() to
57 /// determine if NEON should actually be used.
58 bool UseNEONForSinglePrecisionFP;
60 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
61 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
64 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
65 /// forwarding to allow mul + mla being issued back to back.
66 bool HasVMLxForwarding;
68 /// SlowFPBrcc - True if floating point compare + branch is slow.
71 /// InThumbMode - True if compiling for Thumb, false for ARM.
74 /// HasThumb2 - True if Thumb2 instructions are supported.
77 /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
78 /// v6m, v7m for example.
81 /// NoARM - True if subtarget does not support ARM mode execution.
84 /// PostRAScheduler - True if using post-register-allocation scheduler.
87 /// IsR9Reserved - True if R9 is a not available as general purpose register.
90 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
91 /// imms (including global addresses).
94 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
95 /// must be able to synthesize call stubs for interworking between ARM and
97 bool SupportsTailCall;
99 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
103 /// HasD16 - True if subtarget is limited to 16 double precision
104 /// FP registers for VFPv3.
107 /// HasHardwareDivide - True if subtarget supports [su]div
108 bool HasHardwareDivide;
110 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
112 bool HasT2ExtractPack;
114 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
118 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
119 /// over 16-bit ones.
122 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
123 /// that partially update CPSR and add false dependency on the previous
124 /// CPSR setting instruction.
125 bool AvoidCPSRPartialUpdate;
127 /// HasRAS - Some processors perform return stack prediction. CodeGen should
128 /// avoid issue "normal" call instructions to callees which do not return.
131 /// HasMPExtension - True if the subtarget supports Multiprocessing
132 /// extension (ARMv7 only).
135 /// FPOnlySP - If true, the floating point unit only supports single
139 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
140 /// accesses for some types. For details, see
141 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
142 bool AllowsUnalignedMem;
144 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
145 /// and such) instructions in Thumb2 code.
148 /// stackAlignment - The minimum alignment known to hold of the stack frame on
149 /// entry to the function and which must be maintained by every function.
150 unsigned stackAlignment;
152 /// CPUString - String name of used CPU.
153 std::string CPUString;
155 /// TargetTriple - What processor and OS we're targeting.
158 /// Selected instruction itineraries (one entry per itinerary class.)
159 InstrItineraryData InstrItins;
168 ARM_ABI_AAPCS // ARM EABI
171 /// This constructor initializes the data members to match that
172 /// of the specified triple.
174 ARMSubtarget(const std::string &TT, const std::string &CPU,
175 const std::string &FS);
177 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
178 /// that still makes it profitable to inline the call.
179 unsigned getMaxInlineSizeThreshold() const {
180 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
181 // Change this once Thumb1 ldmia / stmia support is added.
182 return isThumb1Only() ? 0 : 64;
184 /// ParseSubtargetFeatures - Parses features string setting specified
185 /// subtarget options. Definition of function is auto generated by tblgen.
186 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
188 void computeIssueWidth();
190 bool hasV4TOps() const { return HasV4TOps; }
191 bool hasV5TOps() const { return HasV5TOps; }
192 bool hasV5TEOps() const { return HasV5TEOps; }
193 bool hasV6Ops() const { return HasV6Ops; }
194 bool hasV6T2Ops() const { return HasV6T2Ops; }
195 bool hasV7Ops() const { return HasV7Ops; }
197 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
198 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
199 bool isCortexM3() const { return CPUString == "cortex-m3"; }
201 bool hasARMOps() const { return !NoARM; }
203 bool hasVFP2() const { return HasVFPv2; }
204 bool hasVFP3() const { return HasVFPv3; }
205 bool hasVFP4() const { return HasVFPv4; }
206 bool hasNEON() const { return HasNEON; }
207 bool useNEONForSinglePrecisionFP() const {
208 return hasNEON() && UseNEONForSinglePrecisionFP; }
210 bool hasDivide() const { return HasHardwareDivide; }
211 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
212 bool hasDataBarrier() const { return HasDataBarrier; }
213 bool useFPVMLx() const { return !SlowFPVMLx; }
214 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
215 bool isFPBrccSlow() const { return SlowFPBrcc; }
216 bool isFPOnlySP() const { return FPOnlySP; }
217 bool prefers32BitThumb() const { return Pref32BitThumb; }
218 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
219 bool hasRAS() const { return HasRAS; }
220 bool hasMPExtension() const { return HasMPExtension; }
221 bool hasThumb2DSP() const { return Thumb2DSP; }
223 bool hasFP16() const { return HasFP16; }
224 bool hasD16() const { return HasD16; }
226 const Triple &getTargetTriple() const { return TargetTriple; }
228 bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
229 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
230 bool isTargetNaCl() const {
231 return TargetTriple.getOS() == Triple::NativeClient;
233 bool isTargetELF() const { return !isTargetDarwin(); }
235 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
236 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
238 bool isThumb() const { return InThumbMode; }
239 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
240 bool isThumb2() const { return InThumbMode && HasThumb2; }
241 bool hasThumb2() const { return HasThumb2; }
242 bool isMClass() const { return IsMClass; }
243 bool isARClass() const { return !IsMClass; }
245 bool isR9Reserved() const { return IsR9Reserved; }
247 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
248 bool supportsTailCall() const { return SupportsTailCall; }
250 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
252 const std::string & getCPUString() const { return CPUString; }
254 unsigned getMispredictionPenalty() const;
256 /// enablePostRAScheduler - True at 'More' optimization.
257 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
258 TargetSubtargetInfo::AntiDepBreakMode& Mode,
259 RegClassVector& CriticalPathRCs) const;
261 /// getInstrItins - Return the instruction itineraies based on subtarget
263 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
265 /// getStackAlignment - Returns the minimum alignment known to hold of the
266 /// stack frame on entry to the function and which must be maintained by every
267 /// function for this subtarget.
268 unsigned getStackAlignment() const { return stackAlignment; }
270 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
272 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
274 } // End llvm namespace
276 #endif // ARMSUBTARGET_H