1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
31 class ARMSubtarget : public ARMGenSubtargetInfo {
33 enum ARMProcFamilyEnum {
34 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
35 CortexR5, Swift, CortexA53, CortexA57, Krait
37 enum ARMProcClassEnum {
38 None, AClass, RClass, MClass
41 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
42 ARMProcFamilyEnum ARMProcFamily;
44 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
45 ARMProcClassEnum ARMProcClass;
47 /// HasV4TOps, HasV5TOps, HasV5TEOps,
48 /// HasV6Ops, HasV6MOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
49 /// Specify whether target support specific ARM ISA variants.
59 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
60 /// floating point ISAs are supported.
67 /// MinSize - True if the function being compiled has the "minsize" attribute
68 /// and should be optimised for size at the expense of speed.
71 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
72 /// specified. Use the method useNEONForSinglePrecisionFP() to
73 /// determine if NEON should actually be used.
74 bool UseNEONForSinglePrecisionFP;
76 /// UseMulOps - True if non-microcoded fused integer multiply-add and
77 /// multiply-subtract instructions should be used.
80 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
81 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
84 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
85 /// forwarding to allow mul + mla being issued back to back.
86 bool HasVMLxForwarding;
88 /// SlowFPBrcc - True if floating point compare + branch is slow.
91 /// InThumbMode - True if compiling for Thumb, false for ARM.
94 /// HasThumb2 - True if Thumb2 instructions are supported.
97 /// NoARM - True if subtarget does not support ARM mode execution.
100 /// PostRAScheduler - True if using post-register-allocation scheduler.
101 bool PostRAScheduler;
103 /// IsR9Reserved - True if R9 is a not available as general purpose register.
106 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
107 /// imms (including global addresses).
110 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
111 /// must be able to synthesize call stubs for interworking between ARM and
113 bool SupportsTailCall;
115 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
119 /// HasD16 - True if subtarget is limited to 16 double precision
120 /// FP registers for VFPv3.
123 /// HasHardwareDivide - True if subtarget supports [su]div
124 bool HasHardwareDivide;
126 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
127 bool HasHardwareDivideInARM;
129 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
131 bool HasT2ExtractPack;
133 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
137 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
138 /// over 16-bit ones.
141 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
142 /// that partially update CPSR and add false dependency on the previous
143 /// CPSR setting instruction.
144 bool AvoidCPSRPartialUpdate;
146 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
147 /// movs with shifter operand (i.e. asr, lsl, lsr).
148 bool AvoidMOVsShifterOperand;
150 /// HasRAS - Some processors perform return stack prediction. CodeGen should
151 /// avoid issue "normal" call instructions to callees which do not return.
154 /// HasMPExtension - True if the subtarget supports Multiprocessing
155 /// extension (ARMv7 only).
158 /// HasVirtualization - True if the subtarget supports the Virtualization
160 bool HasVirtualization;
162 /// FPOnlySP - If true, the floating point unit only supports single
166 /// If true, the processor supports the Performance Monitor Extensions. These
167 /// include a generic cycle-counter as well as more fine-grained (often
168 /// implementation-specific) events.
171 /// HasTrustZone - if true, processor supports TrustZone security extensions
174 /// HasCrypto - if true, processor supports Cryptography extensions
177 /// HasCRC - if true, processor supports CRC instructions
180 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
181 /// particularly effective at zeroing a VFP register.
182 bool HasZeroCycleZeroing;
184 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
185 /// accesses for some types. For details, see
186 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
187 bool AllowsUnalignedMem;
189 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
190 /// blocks to conform to ARMv8 rule.
193 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
194 /// and such) instructions in Thumb2 code.
197 /// NaCl TRAP instruction is generated instead of the regular TRAP.
200 /// Target machine allowed unsafe FP math (such as use of NEON fp)
203 /// stackAlignment - The minimum alignment known to hold of the stack frame on
204 /// entry to the function and which must be maintained by every function.
205 unsigned stackAlignment;
207 /// CPUString - String name of used CPU.
208 std::string CPUString;
210 /// IsLittle - The target is Little Endian
213 /// TargetTriple - What processor and OS we're targeting.
216 /// SchedModel - Processor specific instruction costs.
217 const MCSchedModel *SchedModel;
219 /// Selected instruction itineraries (one entry per itinerary class.)
220 InstrItineraryData InstrItins;
222 /// Options passed via command line that could influence the target
223 const TargetOptions &Options;
229 ARM_ABI_AAPCS // ARM EABI
232 /// This constructor initializes the data members to match that
233 /// of the specified triple.
235 ARMSubtarget(const std::string &TT, const std::string &CPU,
236 const std::string &FS, bool IsLittle,
237 const TargetOptions &Options);
239 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
240 /// that still makes it profitable to inline the call.
241 unsigned getMaxInlineSizeThreshold() const {
244 /// ParseSubtargetFeatures - Parses features string setting specified
245 /// subtarget options. Definition of function is auto generated by tblgen.
246 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
248 /// \brief Reset the features for the ARM target.
249 void resetSubtargetFeatures(const MachineFunction *MF) override;
251 void initializeEnvironment();
252 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
254 void computeIssueWidth();
256 bool hasV4TOps() const { return HasV4TOps; }
257 bool hasV5TOps() const { return HasV5TOps; }
258 bool hasV5TEOps() const { return HasV5TEOps; }
259 bool hasV6Ops() const { return HasV6Ops; }
260 bool hasV6MOps() const { return HasV6MOps; }
261 bool hasV6T2Ops() const { return HasV6T2Ops; }
262 bool hasV7Ops() const { return HasV7Ops; }
263 bool hasV8Ops() const { return HasV8Ops; }
265 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
266 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
267 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
268 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
269 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
270 bool isSwift() const { return ARMProcFamily == Swift; }
271 bool isCortexM3() const { return CPUString == "cortex-m3"; }
272 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
273 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
274 bool isKrait() const { return ARMProcFamily == Krait; }
276 bool hasARMOps() const { return !NoARM; }
278 bool hasVFP2() const { return HasVFPv2; }
279 bool hasVFP3() const { return HasVFPv3; }
280 bool hasVFP4() const { return HasVFPv4; }
281 bool hasFPARMv8() const { return HasFPARMv8; }
282 bool hasNEON() const { return HasNEON; }
283 bool hasCrypto() const { return HasCrypto; }
284 bool hasCRC() const { return HasCRC; }
285 bool hasVirtualization() const { return HasVirtualization; }
286 bool isMinSize() const { return MinSize; }
287 bool useNEONForSinglePrecisionFP() const {
288 return hasNEON() && UseNEONForSinglePrecisionFP; }
290 bool hasDivide() const { return HasHardwareDivide; }
291 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
292 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
293 bool hasDataBarrier() const { return HasDataBarrier; }
294 bool hasAnyDataBarrier() const {
295 return HasDataBarrier || (hasV6Ops() && !isThumb());
297 bool useMulOps() const { return UseMulOps; }
298 bool useFPVMLx() const { return !SlowFPVMLx; }
299 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
300 bool isFPBrccSlow() const { return SlowFPBrcc; }
301 bool isFPOnlySP() const { return FPOnlySP; }
302 bool hasPerfMon() const { return HasPerfMon; }
303 bool hasTrustZone() const { return HasTrustZone; }
304 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
305 bool prefers32BitThumb() const { return Pref32BitThumb; }
306 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
307 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
308 bool hasRAS() const { return HasRAS; }
309 bool hasMPExtension() const { return HasMPExtension; }
310 bool hasThumb2DSP() const { return Thumb2DSP; }
311 bool useNaClTrap() const { return UseNaClTrap; }
313 bool hasFP16() const { return HasFP16; }
314 bool hasD16() const { return HasD16; }
316 const Triple &getTargetTriple() const { return TargetTriple; }
318 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
319 bool isTargetIOS() const { return TargetTriple.isiOS(); }
320 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
321 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
322 bool isTargetNetBSD() const { return TargetTriple.getOS() == Triple::NetBSD; }
323 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
325 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
326 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
327 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
329 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
330 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
331 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
332 // even for GNUEABI, so we can make a distinction here and still conform to
333 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
334 // FIXME: The Darwin exception is temporary, while we move users to
335 // "*-*-*-macho" triples as quickly as possible.
336 bool isTargetAEABI() const {
337 return (TargetTriple.getEnvironment() == Triple::EABI ||
338 TargetTriple.getEnvironment() == Triple::EABIHF) &&
339 !isTargetDarwin() && !isTargetWindows();
342 // ARM Targets that support EHABI exception handling standard
343 // Darwin uses SjLj. Other targets might need more checks.
344 bool isTargetEHABICompatible() const {
345 return (TargetTriple.getEnvironment() == Triple::EABI ||
346 TargetTriple.getEnvironment() == Triple::GNUEABI ||
347 TargetTriple.getEnvironment() == Triple::EABIHF ||
348 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
349 TargetTriple.getEnvironment() == Triple::Android) &&
350 !isTargetDarwin() && !isTargetWindows();
353 bool isTargetHardFloat() const {
354 // FIXME: this is invalid for WindowsCE
355 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
356 TargetTriple.getEnvironment() == Triple::EABIHF ||
359 bool isTargetAndroid() const {
360 return TargetTriple.getEnvironment() == Triple::Android;
363 bool isAPCS_ABI() const {
364 assert(TargetABI != ARM_ABI_UNKNOWN);
365 return TargetABI == ARM_ABI_APCS;
367 bool isAAPCS_ABI() const {
368 assert(TargetABI != ARM_ABI_UNKNOWN);
369 return TargetABI == ARM_ABI_AAPCS;
372 bool isThumb() const { return InThumbMode; }
373 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
374 bool isThumb2() const { return InThumbMode && HasThumb2; }
375 bool hasThumb2() const { return HasThumb2; }
376 bool isMClass() const { return ARMProcClass == MClass; }
377 bool isRClass() const { return ARMProcClass == RClass; }
378 bool isAClass() const { return ARMProcClass == AClass; }
380 bool isR9Reserved() const { return IsR9Reserved; }
382 bool useMovt() const { return UseMovt && !isMinSize(); }
383 bool supportsTailCall() const { return SupportsTailCall; }
385 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
387 bool restrictIT() const { return RestrictIT; }
389 const std::string & getCPUString() const { return CPUString; }
391 bool isLittle() const { return IsLittle; }
393 unsigned getMispredictionPenalty() const;
395 /// This function returns true if the target has sincos() routine in its
396 /// compiler runtime or math libraries.
397 bool hasSinCos() const;
399 /// enablePostRAScheduler - True at 'More' optimization.
400 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
401 TargetSubtargetInfo::AntiDepBreakMode& Mode,
402 RegClassVector& CriticalPathRCs) const override;
404 /// getInstrItins - Return the instruction itineraies based on subtarget
406 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
408 /// getStackAlignment - Returns the minimum alignment known to hold of the
409 /// stack frame on entry to the function and which must be maintained by every
410 /// function for this subtarget.
411 unsigned getStackAlignment() const { return stackAlignment; }
413 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
415 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
417 } // End llvm namespace
419 #endif // ARMSUBTARGET_H