1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
18 #include "ARMFrameLowering.h"
19 #include "ARMISelLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMMCTargetDesc.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/MC/MCInstrItineraries.h"
30 #include "llvm/Target/TargetSubtargetInfo.h"
33 #define GET_SUBTARGETINFO_HEADER
34 #include "ARMGenSubtargetInfo.inc"
40 class ARMBaseTargetMachine;
42 class ARMSubtarget : public ARMGenSubtargetInfo {
44 enum ARMProcFamilyEnum {
45 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
46 CortexA17, CortexR4, CortexR4F, CortexR5, Swift, CortexA53, CortexA57, Krait,
48 enum ARMProcClassEnum {
49 None, AClass, RClass, MClass
52 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
53 ARMProcFamilyEnum ARMProcFamily;
55 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
56 ARMProcClassEnum ARMProcClass;
58 /// HasV4TOps, HasV5TOps, HasV5TEOps,
59 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
60 /// Specify whether target support specific ARM ISA variants.
72 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
73 /// floating point ISAs are supported.
80 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
81 /// specified. Use the method useNEONForSinglePrecisionFP() to
82 /// determine if NEON should actually be used.
83 bool UseNEONForSinglePrecisionFP;
85 /// UseMulOps - True if non-microcoded fused integer multiply-add and
86 /// multiply-subtract instructions should be used.
89 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
90 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
93 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
94 /// forwarding to allow mul + mla being issued back to back.
95 bool HasVMLxForwarding;
97 /// SlowFPBrcc - True if floating point compare + branch is slow.
100 /// InThumbMode - True if compiling for Thumb, false for ARM.
103 /// UseSoftFloat - True if we're using software floating point features.
106 /// HasThumb2 - True if Thumb2 instructions are supported.
109 /// NoARM - True if subtarget does not support ARM mode execution.
112 /// IsR9Reserved - True if R9 is a not available as general purpose register.
115 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
116 /// imms (including global addresses).
119 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
120 /// must be able to synthesize call stubs for interworking between ARM and
122 bool SupportsTailCall;
124 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
128 /// HasD16 - True if subtarget is limited to 16 double precision
129 /// FP registers for VFPv3.
132 /// HasHardwareDivide - True if subtarget supports [su]div
133 bool HasHardwareDivide;
135 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
136 bool HasHardwareDivideInARM;
138 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
140 bool HasT2ExtractPack;
142 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
146 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
147 /// over 16-bit ones.
150 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
151 /// that partially update CPSR and add false dependency on the previous
152 /// CPSR setting instruction.
153 bool AvoidCPSRPartialUpdate;
155 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
156 /// movs with shifter operand (i.e. asr, lsl, lsr).
157 bool AvoidMOVsShifterOperand;
159 /// HasRAS - Some processors perform return stack prediction. CodeGen should
160 /// avoid issue "normal" call instructions to callees which do not return.
163 /// HasMPExtension - True if the subtarget supports Multiprocessing
164 /// extension (ARMv7 only).
167 /// HasVirtualization - True if the subtarget supports the Virtualization
169 bool HasVirtualization;
171 /// FPOnlySP - If true, the floating point unit only supports single
175 /// If true, the processor supports the Performance Monitor Extensions. These
176 /// include a generic cycle-counter as well as more fine-grained (often
177 /// implementation-specific) events.
180 /// HasTrustZone - if true, processor supports TrustZone security extensions
183 /// HasCrypto - if true, processor supports Cryptography extensions
186 /// HasCRC - if true, processor supports CRC instructions
189 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
190 /// particularly effective at zeroing a VFP register.
191 bool HasZeroCycleZeroing;
193 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
194 /// accesses for some types. For details, see
195 /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
196 bool AllowsUnalignedMem;
198 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
199 /// blocks to conform to ARMv8 rule.
202 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
203 /// and such) instructions in Thumb2 code.
206 /// NaCl TRAP instruction is generated instead of the regular TRAP.
209 /// Target machine allowed unsafe FP math (such as use of NEON fp)
212 /// stackAlignment - The minimum alignment known to hold of the stack frame on
213 /// entry to the function and which must be maintained by every function.
214 unsigned stackAlignment;
216 /// CPUString - String name of used CPU.
217 std::string CPUString;
219 /// IsLittle - The target is Little Endian
222 /// TargetTriple - What processor and OS we're targeting.
225 /// SchedModel - Processor specific instruction costs.
226 MCSchedModel SchedModel;
228 /// Selected instruction itineraries (one entry per itinerary class.)
229 InstrItineraryData InstrItins;
231 /// Options passed via command line that could influence the target
232 const TargetOptions &Options;
234 const ARMBaseTargetMachine &TM;
237 /// This constructor initializes the data members to match that
238 /// of the specified triple.
240 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
241 const ARMBaseTargetMachine &TM, bool IsLittle);
243 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
244 /// that still makes it profitable to inline the call.
245 unsigned getMaxInlineSizeThreshold() const {
248 /// ParseSubtargetFeatures - Parses features string setting specified
249 /// subtarget options. Definition of function is auto generated by tblgen.
250 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
252 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
253 /// so that we can use initializer lists for subtarget initialization.
254 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
256 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
259 const ARMBaseInstrInfo *getInstrInfo() const override {
260 return InstrInfo.get();
262 const ARMTargetLowering *getTargetLowering() const override {
265 const ARMFrameLowering *getFrameLowering() const override {
266 return FrameLowering.get();
268 const ARMBaseRegisterInfo *getRegisterInfo() const override {
269 return &InstrInfo->getRegisterInfo();
273 ARMSelectionDAGInfo TSInfo;
274 // Either Thumb1FrameLowering or ARMFrameLowering.
275 std::unique_ptr<ARMFrameLowering> FrameLowering;
276 // Either Thumb1InstrInfo or Thumb2InstrInfo.
277 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
278 ARMTargetLowering TLInfo;
280 void initializeEnvironment();
281 void initSubtargetFeatures(StringRef CPU, StringRef FS);
282 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
285 void computeIssueWidth();
287 bool hasV4TOps() const { return HasV4TOps; }
288 bool hasV5TOps() const { return HasV5TOps; }
289 bool hasV5TEOps() const { return HasV5TEOps; }
290 bool hasV6Ops() const { return HasV6Ops; }
291 bool hasV6MOps() const { return HasV6MOps; }
292 bool hasV6KOps() const { return HasV6KOps; }
293 bool hasV6T2Ops() const { return HasV6T2Ops; }
294 bool hasV7Ops() const { return HasV7Ops; }
295 bool hasV8Ops() const { return HasV8Ops; }
296 bool hasV8_1aOps() const { return HasV8_1aOps; }
298 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
299 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
300 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
301 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
302 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
303 bool isSwift() const { return ARMProcFamily == Swift; }
304 bool isCortexM3() const { return CPUString == "cortex-m3"; }
305 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
306 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
307 bool isKrait() const { return ARMProcFamily == Krait; }
309 bool hasARMOps() const { return !NoARM; }
311 bool hasVFP2() const { return HasVFPv2; }
312 bool hasVFP3() const { return HasVFPv3; }
313 bool hasVFP4() const { return HasVFPv4; }
314 bool hasFPARMv8() const { return HasFPARMv8; }
315 bool hasNEON() const { return HasNEON; }
316 bool hasCrypto() const { return HasCrypto; }
317 bool hasCRC() const { return HasCRC; }
318 bool hasVirtualization() const { return HasVirtualization; }
319 bool useNEONForSinglePrecisionFP() const {
320 return hasNEON() && UseNEONForSinglePrecisionFP;
323 bool hasDivide() const { return HasHardwareDivide; }
324 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
325 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
326 bool hasDataBarrier() const { return HasDataBarrier; }
327 bool hasAnyDataBarrier() const {
328 return HasDataBarrier || (hasV6Ops() && !isThumb());
330 bool useMulOps() const { return UseMulOps; }
331 bool useFPVMLx() const { return !SlowFPVMLx; }
332 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
333 bool isFPBrccSlow() const { return SlowFPBrcc; }
334 bool isFPOnlySP() const { return FPOnlySP; }
335 bool hasPerfMon() const { return HasPerfMon; }
336 bool hasTrustZone() const { return HasTrustZone; }
337 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
338 bool prefers32BitThumb() const { return Pref32BitThumb; }
339 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
340 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
341 bool hasRAS() const { return HasRAS; }
342 bool hasMPExtension() const { return HasMPExtension; }
343 bool hasThumb2DSP() const { return Thumb2DSP; }
344 bool useNaClTrap() const { return UseNaClTrap; }
346 bool hasFP16() const { return HasFP16; }
347 bool hasD16() const { return HasD16; }
349 const Triple &getTargetTriple() const { return TargetTriple; }
351 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
352 bool isTargetIOS() const { return TargetTriple.isiOS(); }
353 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
354 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
355 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
356 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
358 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
359 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
360 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
362 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
363 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
364 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
365 // even for GNUEABI, so we can make a distinction here and still conform to
366 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
367 // FIXME: The Darwin exception is temporary, while we move users to
368 // "*-*-*-macho" triples as quickly as possible.
369 bool isTargetAEABI() const {
370 return (TargetTriple.getEnvironment() == Triple::EABI ||
371 TargetTriple.getEnvironment() == Triple::EABIHF) &&
372 !isTargetDarwin() && !isTargetWindows();
375 // ARM Targets that support EHABI exception handling standard
376 // Darwin uses SjLj. Other targets might need more checks.
377 bool isTargetEHABICompatible() const {
378 return (TargetTriple.getEnvironment() == Triple::EABI ||
379 TargetTriple.getEnvironment() == Triple::GNUEABI ||
380 TargetTriple.getEnvironment() == Triple::EABIHF ||
381 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
382 TargetTriple.getEnvironment() == Triple::Android) &&
383 !isTargetDarwin() && !isTargetWindows();
386 bool isTargetHardFloat() const {
387 // FIXME: this is invalid for WindowsCE
388 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
389 TargetTriple.getEnvironment() == Triple::EABIHF ||
392 bool isTargetAndroid() const {
393 return TargetTriple.getEnvironment() == Triple::Android;
396 bool isAPCS_ABI() const;
397 bool isAAPCS_ABI() const;
399 bool useSoftFloat() const { return UseSoftFloat; }
400 bool isThumb() const { return InThumbMode; }
401 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
402 bool isThumb2() const { return InThumbMode && HasThumb2; }
403 bool hasThumb2() const { return HasThumb2; }
404 bool isMClass() const { return ARMProcClass == MClass; }
405 bool isRClass() const { return ARMProcClass == RClass; }
406 bool isAClass() const { return ARMProcClass == AClass; }
409 return isThumb1Only() && isMClass();
412 bool isR9Reserved() const { return IsR9Reserved; }
414 bool useMovt(const MachineFunction &MF) const;
416 bool supportsTailCall() const { return SupportsTailCall; }
418 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
420 bool restrictIT() const { return RestrictIT; }
422 const std::string & getCPUString() const { return CPUString; }
424 bool isLittle() const { return IsLittle; }
426 unsigned getMispredictionPenalty() const;
428 /// This function returns true if the target has sincos() routine in its
429 /// compiler runtime or math libraries.
430 bool hasSinCos() const;
432 /// True for some subtargets at > -O0.
433 bool enablePostRAScheduler() const override;
435 // enableAtomicExpand- True if we need to expand our atomics.
436 bool enableAtomicExpand() const override;
438 /// getInstrItins - Return the instruction itineraries based on subtarget
440 const InstrItineraryData *getInstrItineraryData() const override {
444 /// getStackAlignment - Returns the minimum alignment known to hold of the
445 /// stack frame on entry to the function and which must be maintained by every
446 /// function for this subtarget.
447 unsigned getStackAlignment() const { return stackAlignment; }
449 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
451 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
453 /// True if fast-isel is used.
454 bool useFastISel() const;
456 } // End llvm namespace
458 #endif // ARMSUBTARGET_H