1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMTargetMachine.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
30 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
31 cl::desc("Inhibit optimization of S->D register accesses on A15"),
35 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
36 cl::desc("Run SimplifyCFG after expanding atomic operations"
37 " to make use of cmpxchg flow-based information"),
41 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
42 cl::desc("Enable ARM load/store optimization pass"),
45 // FIXME: Unify control over GlobalMerge.
46 static cl::opt<cl::boolOrDefault>
47 EnableGlobalMerge("arm-global-merge", cl::Hidden,
48 cl::desc("Enable the global merge pass"));
50 extern "C" void LLVMInitializeARMTarget() {
51 // Register the target.
52 RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
53 RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
54 RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
55 RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
58 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
59 if (TT.isOSBinFormatMachO())
60 return make_unique<TargetLoweringObjectFileMachO>();
62 return make_unique<TargetLoweringObjectFileCOFF>();
63 return make_unique<ARMElfTargetObjectFile>();
66 static ARMBaseTargetMachine::ARMABI
67 computeTargetABI(const Triple &TT, StringRef CPU,
68 const TargetOptions &Options) {
69 if (Options.MCOptions.getABIName().startswith("aapcs"))
70 return ARMBaseTargetMachine::ARM_ABI_AAPCS;
71 else if (Options.MCOptions.getABIName().startswith("apcs"))
72 return ARMBaseTargetMachine::ARM_ABI_APCS;
74 assert(Options.MCOptions.getABIName().empty() &&
75 "Unknown target-abi option!");
77 ARMBaseTargetMachine::ARMABI TargetABI =
78 ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
80 // FIXME: This is duplicated code from the front end and should be unified.
81 if (TT.isOSBinFormatMachO()) {
82 if (TT.getEnvironment() == llvm::Triple::EABI ||
83 (TT.getOS() == llvm::Triple::UnknownOS && TT.isOSBinFormatMachO()) ||
84 CPU.startswith("cortex-m")) {
85 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
87 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
89 } else if (TT.isOSWindows()) {
90 // FIXME: this is invalid for WindowsCE
91 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
93 // Select the default based on the platform.
94 switch (TT.getEnvironment()) {
95 case llvm::Triple::Android:
96 case llvm::Triple::GNUEABI:
97 case llvm::Triple::GNUEABIHF:
98 case llvm::Triple::EABIHF:
99 case llvm::Triple::EABI:
100 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
102 case llvm::Triple::GNU:
103 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
107 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
109 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
117 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
118 const TargetOptions &Options,
120 auto ABI = computeTargetABI(TT, CPU, Options);
121 std::string Ret = "";
130 Ret += DataLayout::getManglingComponent(TT);
132 // Pointers are 32 bits and aligned to 32 bits.
135 // ABIs other than APCS have 64 bit integers with natural alignment.
136 if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
139 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
140 // bits, others to 64 bits. We always try to align to 64 bits.
141 if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
144 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
145 // to 64. We always ty to give them natural alignment.
146 if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
147 Ret += "-v64:32:64-v128:32:128";
149 Ret += "-v128:64:128";
151 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
152 // particular hardware support on 32-bit ARM).
155 // Integer registers are 32 bits.
158 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
159 // aligned everywhere else.
162 else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
170 /// TargetMachine ctor - Create an ARM architecture model.
172 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
173 StringRef CPU, StringRef FS,
174 const TargetOptions &Options,
175 Reloc::Model RM, CodeModel::Model CM,
176 CodeGenOpt::Level OL, bool isLittle)
177 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
178 CPU, FS, Options, RM, CM, OL),
179 TargetABI(computeTargetABI(TT, CPU, Options)),
180 TLOF(createTLOF(getTargetTriple())),
181 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
183 // Default to triple-appropriate float ABI
184 if (Options.FloatABIType == FloatABI::Default)
185 this->Options.FloatABIType =
186 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
189 ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
192 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
193 Attribute CPUAttr = F.getFnAttribute("target-cpu");
194 Attribute FSAttr = F.getFnAttribute("target-features");
196 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
197 ? CPUAttr.getValueAsString().str()
199 std::string FS = !FSAttr.hasAttribute(Attribute::None)
200 ? FSAttr.getValueAsString().str()
203 // FIXME: This is related to the code below to reset the target options,
204 // we need to know whether or not the soft float flag is set on the
205 // function before we can generate a subtarget. We also need to use
206 // it as a key for the subtarget since that can be the only difference
207 // between two functions.
209 F.hasFnAttribute("use-soft-float") &&
210 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
211 // If the soft float attribute is set on the function turn on the soft float
212 // subtarget feature.
214 FS += FS.empty() ? "+soft-float" : ",+soft-float";
216 auto &I = SubtargetMap[CPU + FS];
218 // This needs to be done before we create a new subtarget since any
219 // creation will depend on the TM and the code generation flags on the
220 // function that reside in TargetOptions.
221 resetTargetOptions(F);
222 I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
227 TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
228 return TargetIRAnalysis(
229 [this](Function &F) { return TargetTransformInfo(ARMTTIImpl(this, F)); });
233 void ARMTargetMachine::anchor() { }
235 ARMTargetMachine::ARMTargetMachine(const Target &T, const Triple &TT,
236 StringRef CPU, StringRef FS,
237 const TargetOptions &Options,
238 Reloc::Model RM, CodeModel::Model CM,
239 CodeGenOpt::Level OL, bool isLittle)
240 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
242 if (!Subtarget.hasARMOps())
243 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
244 "support ARM mode execution!");
247 void ARMLETargetMachine::anchor() { }
249 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
250 StringRef CPU, StringRef FS,
251 const TargetOptions &Options,
252 Reloc::Model RM, CodeModel::Model CM,
253 CodeGenOpt::Level OL)
254 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
256 void ARMBETargetMachine::anchor() { }
258 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
259 StringRef CPU, StringRef FS,
260 const TargetOptions &Options,
261 Reloc::Model RM, CodeModel::Model CM,
262 CodeGenOpt::Level OL)
263 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
265 void ThumbTargetMachine::anchor() { }
267 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const Triple &TT,
268 StringRef CPU, StringRef FS,
269 const TargetOptions &Options,
270 Reloc::Model RM, CodeModel::Model CM,
271 CodeGenOpt::Level OL, bool isLittle)
272 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
276 void ThumbLETargetMachine::anchor() { }
278 ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, const Triple &TT,
279 StringRef CPU, StringRef FS,
280 const TargetOptions &Options,
281 Reloc::Model RM, CodeModel::Model CM,
282 CodeGenOpt::Level OL)
283 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
285 void ThumbBETargetMachine::anchor() { }
287 ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, const Triple &TT,
288 StringRef CPU, StringRef FS,
289 const TargetOptions &Options,
290 Reloc::Model RM, CodeModel::Model CM,
291 CodeGenOpt::Level OL)
292 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
295 /// ARM Code Generator Pass Configuration Options.
296 class ARMPassConfig : public TargetPassConfig {
298 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
299 : TargetPassConfig(TM, PM) {}
301 ARMBaseTargetMachine &getARMTargetMachine() const {
302 return getTM<ARMBaseTargetMachine>();
305 void addIRPasses() override;
306 bool addPreISel() override;
307 bool addInstSelector() override;
308 void addPreRegAlloc() override;
309 void addPreSched2() override;
310 void addPreEmitPass() override;
314 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
315 return new ARMPassConfig(this, PM);
318 void ARMPassConfig::addIRPasses() {
319 if (TM->Options.ThreadModel == ThreadModel::Single)
320 addPass(createLowerAtomicPass());
322 addPass(createAtomicExpandPass(TM));
324 // Cmpxchg instructions are often used with a subsequent comparison to
325 // determine whether it succeeded. We can exploit existing control-flow in
326 // ldrex/strex loops to simplify this, but it needs tidying up.
327 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
328 addPass(createCFGSimplificationPass(-1, [this](const Function &F) {
329 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
330 return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
333 TargetPassConfig::addIRPasses();
335 // Match interleaved memory accesses to ldN/stN intrinsics.
336 if (TM->getOptLevel() != CodeGenOpt::None)
337 addPass(createInterleavedAccessPass(TM));
340 bool ARMPassConfig::addPreISel() {
341 if ((TM->getOptLevel() != CodeGenOpt::None &&
342 EnableGlobalMerge == cl::BOU_UNSET) ||
343 EnableGlobalMerge == cl::BOU_TRUE) {
344 // FIXME: This is using the thumb1 only constant value for
345 // maximal global offset for merging globals. We may want
346 // to look into using the old value for non-thumb1 code of
347 // 4095 based on the TargetMachine, but this starts to become
348 // tricky when doing code gen per function.
349 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
350 (EnableGlobalMerge == cl::BOU_UNSET);
351 // Merging of extern globals is enabled by default on non-Mach-O as we
352 // expect it to be generally either beneficial or harmless. On Mach-O it
353 // is disabled as we emit the .subsections_via_symbols directive which
354 // means that merging extern globals is not safe.
355 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
356 addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
357 MergeExternalByDefault));
363 bool ARMPassConfig::addInstSelector() {
364 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
366 if (TM->getTargetTriple().isOSBinFormatELF() && TM->Options.EnableFastISel)
367 addPass(createARMGlobalBaseRegPass());
371 void ARMPassConfig::addPreRegAlloc() {
372 if (getOptLevel() != CodeGenOpt::None) {
373 addPass(createMLxExpansionPass());
375 if (EnableARMLoadStoreOpt)
376 addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
378 if (!DisableA15SDOptimization)
379 addPass(createA15SDOptimizerPass());
383 void ARMPassConfig::addPreSched2() {
384 if (getOptLevel() != CodeGenOpt::None) {
385 if (EnableARMLoadStoreOpt)
386 addPass(createARMLoadStoreOptimizationPass());
388 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
391 // Expand some pseudo instructions into multiple instructions to allow
392 // proper scheduling.
393 addPass(createARMExpandPseudoPass());
395 if (getOptLevel() != CodeGenOpt::None) {
396 // in v8, IfConversion depends on Thumb instruction widths
397 addPass(createThumb2SizeReductionPass([this](const Function &F) {
398 return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
401 addPass(createIfConverter([this](const Function &F) {
402 return !this->TM->getSubtarget<ARMSubtarget>(F).isThumb1Only();
405 addPass(createThumb2ITBlockPass());
408 void ARMPassConfig::addPreEmitPass() {
409 addPass(createThumb2SizeReductionPass());
411 // Constant island pass work on unbundled instructions.
412 addPass(createUnpackMachineBundles([this](const Function &F) {
413 return this->TM->getSubtarget<ARMSubtarget>(F).isThumb2();
416 // Don't optimize barriers at -O0.
417 if (getOptLevel() != CodeGenOpt::None)
418 addPass(createARMOptimizeBarriersPass());
420 addPass(createARMConstantIslandPass());