1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
15 #include "ARMFrameLowering.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 EnableGlobalMerge("global-merge", cl::Hidden,
28 cl::desc("Enable global merge pass"),
32 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
33 cl::desc("Inhibit optimization of S->D register accesses on A15"),
36 extern "C" void LLVMInitializeARMTarget() {
37 // Register the target.
38 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
39 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
43 /// TargetMachine ctor - Create an ARM architecture model.
45 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
46 StringRef CPU, StringRef FS,
47 const TargetOptions &Options,
48 Reloc::Model RM, CodeModel::Model CM,
50 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
51 Subtarget(TT, CPU, FS, Options),
53 InstrItins(Subtarget.getInstrItineraryData()) {
54 // Default to soft float ABI
55 if (Options.FloatABIType == FloatABI::Default)
56 this->Options.FloatABIType = FloatABI::Soft;
59 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
60 // Add first the target-independent BasicTTI pass, then our ARM pass. This
61 // allows the ARM pass to delegate to the target independent layer when
63 PM.add(createBasicTargetTransformInfoPass(this));
64 PM.add(createARMTargetTransformInfoPass(this));
68 void ARMTargetMachine::anchor() { }
70 static std::string computeDataLayout(ARMSubtarget &ST) {
71 // Little endian. Pointers are 32 bits and aligned to 32 bits.
72 std::string Ret = "e-p:32:32";
74 // We have 64 bits floats and integers. The APCS ABI requires them to be
75 // aligned s them to 32 bits, others to 64 bits. We always try to align to
78 Ret += "-f64:32:64-i64:32:64";
80 Ret += "-f64:64:64-i64:64:64";
82 // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
85 Ret += "-i16:16:32-i8:8:32-i1:8:32";
87 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
88 // to 64. We always ty to give them natural alignment.
90 Ret += "-v128:32:128-v64:32:64";
92 Ret += "-v128:64:128-v64:64:64";
94 // An aggregate of size 0 is ABI aligned to 0.
95 // FIXME: explain better what this means.
99 // Integer registers are 32 bits.
102 // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
103 if (ST.isAAPCS_ABI())
111 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
112 StringRef CPU, StringRef FS,
113 const TargetOptions &Options,
114 Reloc::Model RM, CodeModel::Model CM,
115 CodeGenOpt::Level OL)
116 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
117 InstrInfo(Subtarget),
118 DL(computeDataLayout(Subtarget)),
121 FrameLowering(Subtarget) {
123 if (!Subtarget.hasARMOps())
124 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
125 "support ARM mode execution!");
128 void ThumbTargetMachine::anchor() { }
130 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
131 StringRef CPU, StringRef FS,
132 const TargetOptions &Options,
133 Reloc::Model RM, CodeModel::Model CM,
134 CodeGenOpt::Level OL)
135 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
136 InstrInfo(Subtarget.hasThumb2()
137 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
138 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
139 DL(computeDataLayout(Subtarget)),
142 FrameLowering(Subtarget.hasThumb2()
143 ? new ARMFrameLowering(Subtarget)
144 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
149 /// ARM Code Generator Pass Configuration Options.
150 class ARMPassConfig : public TargetPassConfig {
152 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
153 : TargetPassConfig(TM, PM) {}
155 ARMBaseTargetMachine &getARMTargetMachine() const {
156 return getTM<ARMBaseTargetMachine>();
159 const ARMSubtarget &getARMSubtarget() const {
160 return *getARMTargetMachine().getSubtargetImpl();
163 virtual bool addPreISel();
164 virtual bool addInstSelector();
165 virtual bool addPreRegAlloc();
166 virtual bool addPreSched2();
167 virtual bool addPreEmitPass();
171 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
172 return new ARMPassConfig(this, PM);
175 bool ARMPassConfig::addPreISel() {
176 if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
177 addPass(createGlobalMergePass(TM));
182 bool ARMPassConfig::addInstSelector() {
183 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
185 const ARMSubtarget *Subtarget = &getARMSubtarget();
186 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
187 TM->Options.EnableFastISel)
188 addPass(createARMGlobalBaseRegPass());
192 bool ARMPassConfig::addPreRegAlloc() {
193 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
194 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
195 addPass(createARMLoadStoreOptimizationPass(true));
196 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
197 addPass(createMLxExpansionPass());
198 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
199 // enabled when NEON is available.
200 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
201 getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
202 addPass(createA15SDOptimizerPass());
207 bool ARMPassConfig::addPreSched2() {
208 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
209 if (getOptLevel() != CodeGenOpt::None) {
210 if (!getARMSubtarget().isThumb1Only()) {
211 addPass(createARMLoadStoreOptimizationPass());
212 printAndVerify("After ARM load / store optimizer");
214 if (getARMSubtarget().hasNEON())
215 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
218 // Expand some pseudo instructions into multiple instructions to allow
219 // proper scheduling.
220 addPass(createARMExpandPseudoPass());
222 if (getOptLevel() != CodeGenOpt::None) {
223 if (!getARMSubtarget().isThumb1Only()) {
224 // in v8, IfConversion depends on Thumb instruction widths
225 if (getARMSubtarget().restrictIT() &&
226 !getARMSubtarget().prefers32BitThumb())
227 addPass(createThumb2SizeReductionPass());
228 addPass(&IfConverterID);
231 if (getARMSubtarget().isThumb2())
232 addPass(createThumb2ITBlockPass());
237 bool ARMPassConfig::addPreEmitPass() {
238 if (getARMSubtarget().isThumb2()) {
239 if (!getARMSubtarget().prefers32BitThumb())
240 addPass(createThumb2SizeReductionPass());
242 // Constant island pass work on unbundled instructions.
243 addPass(&UnpackMachineBundlesID);
246 addPass(createARMConstantIslandPass());
251 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
252 JITCodeEmitter &JCE) {
253 // Machine code emitter pass for ARM.
254 PM.add(createARMJITCodeEmitterPass(*this, JCE));